One transistor SOI non-volatile random access memory cell

• US 20050026353A1
• Filed: 08/31/2004
• Published: 02/03/2005
• Est. Priority Date: 08/30/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bhattacharyya, Arup
• Granted Patent: US 7,184,312 B2
• Time in Patent Office: Days
• US Class Current: 438/232
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 2207/063 Current sense amplifiers
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/78612 for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

One aspect of the present subject matter relates to a memory cell, or more specifically, to a one-transistor SOI non-volatile memory cell. In various embodiments, the memory cell includes a substrate, a buried insulator layer formed on the substrate, and a transistor formed on the buried insulator layer. The transistor includes a floating body region that includes a charge trapping material. A memory state of the memory cell is determined by trapped charges or neutralized charges in the charge trapping material. The transistor further includes a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region. The transistor further includes a gate insulator layer formed over the channel region, and a gate formed over the gate insulator layer. Other aspects are provided herein.

Claims

1. A method for operating a non-volatile memory cell that includes a silicon-on-insulator field effect transistor that has a floating body region with a charge trapping region, the method comprising:

writing the memory cell into a first memory state by trapping charges in the charge trapping region to provide the SOI-FET with a first threshold voltage, wherein writing the memory cell into a first memory state includes providing a negative word line pulse and a negative bit line pulse;

writing the memory cell into a second memory state by neutralizing charges in the charge trapping region to provide the SOI-FET with a second threshold voltage, wherein writing the memory cell into a second memory state includes providing a positive word line pulse and a negative bit line pulse; and

reading the memory cell using a channel conductance of the SOI-FET to determine a threshold voltage for the SOI-FET.

2. The method of claim 1, wherein:

writing the memory cell into a first memory state further includes providing a negative substrate pulse; and

writing the memory cell into a second memory state further includes providing a positive substrate pulse.

3. A method of operating a non-volatile memory cell that includes a silicon-on-insulator field effect transistor (SOI-FET) that has a floating body region with a floor charge trapping region along at least a portion of an interface between the body region and a buried oxide (BOX) layer, and at least one sidewall charge trapping region along at least one sidewall of the body region, the method comprising:

writing the memory cell into a first memory state, including operating in a field effect transistor (FET) mode in which impact ionization generates excess charges within the floating body region, and trapping the excess charges in the floor and at least one sidewall charge trapping regions to provide the SOI-FET with a first threshold voltage;

reading the memory cell using a channel conductance of the SOI-FET to determine a threshold voltage for the SOI-FET; and

writing the memory cell into a second memory state, including forward biasing a diode formed between the floating body region and a first diffusion region in the SOI-FET to provide an opposite charge in the floating body region to neutralize the charges in the floor and at least one sidewall charge trapping regions and provide the SOI-FET with a second threshold voltage.

4. The method of claim 3, wherein operating in a field effect transistor (FET) mode includes operating the SOI-FET in saturation.

5. The method of claim 3, wherein writing the memory cell into a first memory state further includes applying an EMF field across the floating body region to influence the charges toward the charge trapping region.

6. The method of claim 3, wherein the floor and at least one sidewall charge trapping region includes oxynitride.

7. The method of claim 3, wherein the floor and at least one sidewall charge trapping region includes silicon nitride (Si₃N₄).

8. The method of claim 3, wherein the floor and at least one sidewall charge trapping region includes a silicon rich insulator (SRI).

9. The method of claim 8, wherein the SRI includes silicon-rich-oxide (SRO).

10. The method of claim 8, wherein the SRI includes silicon-rich-nitride (SRN) A4. The method of claim A, wherein the at least one sidewall charge trapping region includes three sidewalls in a u-shaped configuration around a diffusion region.

11. The method of claim 3, wherein the at least one sidewall charge trapping region includes three sidewalls in a u-shaped configuration around a diffusion region without interfering with a channel region.

12. A method of operating a non-volatile memory cell that includes a silicon-on-insulator n-channel field effect transistor (SOI-NFET) that has a floating body region with a floor oxynitride along at least a portion of an interface between the body region and a buried oxide (BOX) layer, and at least one sidewall oxynitride along at least one sidewall of the body region, the method comprising:

writing the memory cell into a first memory state, including operating in a field effect transistor (FET) mode in which impact ionization generates excess holes within the floating body region, and trapping the excess charges in the floor and at least one sidewall oxynitride to provide the SOI-NFET with a first threshold voltage;

reading the memory cell using a channel conductance of the SOI-NFET to determine a threshold voltage for the SOI-NFET; and

writing the memory cell into a second memory state, including forward biasing a diode formed between the floating body region and a first diffusion region in the SOI-NFET to provide electrons in the floating body region to neutralize the holes in the floor and at least one sidewall oxynitride and provide the SOI-FET with a second threshold voltage.

13. The method of claim 12, wherein writing the memory cell into a first memory state further includes applying a negative substrate voltage to provide an EMF field across the floating body region to influence the holes toward the oxynitride.

14. The method of claim 12, wherein writing the memory cell into a second memory state includes applying a negative drain voltage pulse to forward bias a p-n+ junction create an excess negative charge in the body which drift toward and neutralizes holes stored in the oxynitride.

15. The method of claim 12, wherein the oxynitride has a refractive index within a range of approximately 1.75 to 1.9.

16. The method of claim 12, wherein the oxynitride has a refractive index within a range of approximately 1.8 to 1.9.

17. A method of operating a non-volatile memory cell that includes a silicon-on-insulator n-channel field effect transistor (SOI-NFET) that has a floating body region with a floor silicon nitride (Si₃N₄) along at least a portion of an interface between the body region and a buried oxide (BOX) layer, and at least one sidewall silicon nitride (Si₃N₄) along at least one sidewall of the body region, the method comprising:

writing the memory cell into a first memory state, including operating in a field effect transistor (FET) mode in which impact ionization generates excess holes within the floating body region, and trapping the excess charges in the floor and at least one sidewall silicon nitride to provide the SOI-NFET with a first threshold voltage;

reading the memory cell using a channel conductance of the SOI-NFET to determine a threshold voltage for the SOI-NFET; and

writing the memory cell into a second memory state, including forward biasing a diode formed between the floating body region and a first diffusion region in the SOI-NFET to provide electrons in the floating body region to neutralize the holes in the floor and at least one sidewall silicon nitride and provide the SOI-FET with a second threshold voltage.

18. The method of claim 17, wherein writing the memory cell into a first memory state further includes applying a negative substrate voltage to provide an EMF field across the floating body region to influence the holes toward the silicon nitride.

19. The method of claim 17, wherein writing the memory cell into a second memory state includes applying a negative drain voltage pulse to forward bias a p-n+ junction create an excess negative charge in the body which drift toward and neutralizes holes stored in the silicon nitride.

20. A method of operating a non-volatile memory cell that includes a silicon-on-insulator field effect transistor (SOI-FET) that has a floating body region with a floor charge trapping region along at least a portion of an interface between the body region and a buried oxide (BOX) layer, and at least one sidewall charge trapping region along at least one sidewall of the body region, the method comprising:

writing the memory cell into a first memory state, including operating in a bipolar junction transistor (BJT) mode in which applied voltage pulses cause a parasitic BJT device to generate excess charges within the floating body region, and trapping the excess charges in the floor and at least one sidewall charge trapping region to provide the SOI-FET with a first threshold voltage;

reading the memory cell using a channel conductance of the SOI-FET to determine a threshold voltage for the SOI-FET; and

writing the memory cell into a second memory state, including forward biasing a diode formed between the floating body region and a first diffusion region in the SOI-FET to provide an opposite charge in the floating body region to neutralize the charges in the floor and at least one sidewall charge trapping region and provide the SOI-FET with a second threshold voltage.

21. The method of claim 20, wherein the floor and at least one sidewall trapping region includes oxynitride.

22. The method of claim 20, wherein the floor and at least one sidewall trapping region includes silicon nitride (Si₃N₄).

26. The method of claim 20, wherein writing the memory cell into a first memory state includes generating a first drift field to influence the excess charges to the floating body region and writing the memory cell into a second memory state includes generating a second drift field to influence the opposite charge to the floating body region.

27. The method of claim 20, wherein the at least one sidewall charge trapping region includes three sidewalls in a u-shaped configuration around a diffusion region.

23. The method of claim20, wherein the floor and at least one sidewall trapping region includes a silicon-rich-insulator (SRI).

24. The method of claim 23, wherein the SRI includes a silicon-rich-oxide (SRO).

25. The method of claim 23, wherein the SRI includes a silicon-rich-nitride (SRN).

28. A method of operating a non-volatile memory cell that includes a silicon-on-insulator n-channel field effect transistor (SOI-NFET) that includes a parasitic NPN transistor and that has a floating body region with a floor oxynitride along at least a portion of an interface between the body region and a buried oxide (BOX) layer and at least one sidewall oxynitride along at least one sidewall of the body region, the method comprising:

writing the memory cell into a first memory state, including operating in a bipolar junction transistor (BJT) mode in which applied voltage pulses cause the parasitic BJT transistor to generate excess charges within the floating body region, and trapping the excess charges in the floor and at least one sidewall oxynitride to provide the SOI-NFET with a first threshold voltage;

reading the memory cell using a channel conductance of the SOI-NFET to determine a threshold voltage for the SOI-NFET; and

writing the memory cell into a second memory state, including forward biasing a diode formed between the floating body region and a first diffusion region in the SOI-NFET to provide an opposite charge in the floating body region to neutralize the charges in the floor and at least one sidewall oxynitride and provide the SOI-NFET with a second threshold voltage.

29. The method of claim 28, wherein writing the memory cell into a first memory state includes applying a negative gate pulse and a negative drain pulse to forward bias a p-n+ junction and cause the NPN transistor to generate holes near a drain of the SOI-NFET, and applying a negative substrate pulse to influence the generated holes to the oxynitride.

30. The method of claim 28, wherein writing the memory cell into a second memory state includes providing a negative drain pulse and a positive substrate pulse to bias a n+-p diode to generate electrons in the floating body region, and applying a vertical drift field to influence the generated electrons toward the oxynitride.

31. The method of claim 28, wherein the oxynitride has a refractive index within a range of approximately 1.75 to approximately 1.9.

32. The method of claim 28, wherein the oxynitride has a refractive index within a range of approximately 1.8 to approximately 1.9.

33. A method of operating a non-volatile memory cell that includes a silicon-on-insulator n-channel field effect transistor (SOI-NFET) that includes a parasitic NPN transistor and that has a floating body region with a floor silicon nitride (Si₃O₄) along at least a portion of an interface between the body region and a buried oxide (BOX) layer and at least one sidewall silicon nitride (Si₃O₄) along at least one sidewall of the body region, the method comprising:

writing the memory cell into a first memory state, including operating in a bipolar junction transistor (BJT) mode in which applied voltage pulses cause the parasitic BJT transistor to generate excess charges within the floating body region, and trapping the excess charges in the floor and at least one sidewall silicon nitride to provide the SOI-NFET with a first threshold voltage;

reading the memory cell using a channel conductance of the SOI-NFET to determine a threshold voltage for the SOI-NFET; and

writing the memory cell into a second memory state, including forward biasing a diode formed between the floating body region and a first diffusion region in the SOI-NFET to provide an opposite charge in the floating body region to neutralize the charges in the floor and at least one sidewall silicon nitride and provide the SOI-NFET with a second threshold voltage.

34. The method of claim 33, wherein writing the memory cell into a first memory state includes applying a negative gate pulse and a negative drain pulse to forward bias a p-n+ junction and cause the NPN transistor to generate holes near a drain of the SOI-NFET, and applying a negative substrate pulse to influence the generated holes to the silicon nitride.

35. The method of claim 33, wherein writing the memory cell into a second memory state includes providing a negative drain pulse and a positive substrate pulse to bias a n+-p diode to generate electrons in the floating body region, and applying a vertical drift field to influence the generated electrons toward the silicon nitride.