Electron affinity engineered VCSELs
First Claim
1. A VCSEL system comprising:
- a substrate;
a first mirror stack situated on the substrate;
an active region situated on the first mirror stack;
a second mirror stack situated on the active region;
wherein;
the first mirror stack comprises a plurality of pairs of AlAs and GaAs layers;
at least one interface of first and second interfaces, is situated between each AlAs layer and GaAs layer;
the first interface comprises;
a ramp increase of Al from GaAs to AlxGa1-xAs; and
a step increase of Al from AlxGa1-xAs to AlyGa1-yAs, and the second interface comprises;
a step decrease of Al from AlyGa1-yA to AlxGa1-xAs; and
a ramp decrease of Al from AlxGa1-xAs to GaAs.
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Accused Products
Abstract
A VCSEL having an N-type Bragg mirror with alternating layers of high bandgap (low index) and low bandgap (high index) layers of AlGaAs. The layers may be separated by a step change of Al composition followed by a graded region, and vice versa for the next layer, in the N-type mirror to result in a lower and more linear series resistance. Also, an N-type spacer layer may be adjacent to an active region of quantum wells. There may be a similar step in a change of Al composition from the nearest layer of the N-type mirror to the N-type spacer formed from a lower bandgap direct AlGaAs layer to provide lower free carrier absorption. With electron affinity engineering, a minority carrier hole barrier may be inserted adjacent to the quantum wells to improve hole confinement at high current density and high temperature.
121 Citations
38 Claims
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1. A VCSEL system comprising:
-
a substrate;
a first mirror stack situated on the substrate;
an active region situated on the first mirror stack;
a second mirror stack situated on the active region;
wherein;
the first mirror stack comprises a plurality of pairs of AlAs and GaAs layers;
at least one interface of first and second interfaces, is situated between each AlAs layer and GaAs layer;
the first interface comprises;
a ramp increase of Al from GaAs to AlxGa1-xAs; and
a step increase of Al from AlxGa1-xAs to AlyGa1-yAs, and the second interface comprises;
a step decrease of Al from AlyGa1-yA to AlxGa1-xAs; and
a ramp decrease of Al from AlxGa1-xAs to GaAs. - View Dependent Claims (2, 3, 4, 5, 11, 12, 13, 14, 15)
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- 6. The system 5, further comprising a first hole confinement layer situated between the first spacer layer and the active region.
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16. A VCSEL system comprising:
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a first mirror; and
wherein;
the first mirror comprises a plurality of pairs of layers;
each pair of layers of the plurality of pairs has a first layer and a second layer;
the first layer comprises AxB1-xC;
the second layer comprises AyB1-yC;
x+y=1;
a transition layer is situated between each first layer and a second layer;
the transition layer, in a direction of a first layer to a second layer, has a ramp change from x to P|x−
y| and a step change from P|x−
y| to y,the transition layer in a direction of a second layer to a first layer, has a step change from y to P|x−
y| and a ramp change from P|x−
y| to x; and
P≦
1. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
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33. A VCSEL system comprising:
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a first mirror; and
wherein;
the first mirror comprises a plurality of pairs of layers;
each pair of layers has a first layer and a second layer;
the first layer comprises AxC;
the second layer comprises AyC;
x+y=1;
a transition layer is situated between each first layer and a second layer;
the transition layer, in a direction of a first layer to a second layer, has a first change from x to P|x−
y|, and a second change from P|x−
y| to y;
the transition layer in a direction of a second layer to a first layer, has a third change from y to P|x−
y|, and fourth change from P|x−
y| to x; and
P≦
1. - View Dependent Claims (34, 35, 36)
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37. A VCSEL system comprising:
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a substrate;
a first mirror stack situated on the substrate;
an active region situated on the first mirror stack;
a second mirror stack situated on the active region;
wherein;
the first mirror stack comprises a plurality of pairs of AlxGa1-xAs and AlyGa1-yAs layers;
an interface between each AlxGa1-xAs layer and AlyGa1-yAs layer;
the interface comprises;
at least one ramp change of Al composition; and
at least one step change of Al composition.
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38. A system comprising:
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at least one semiconductor stack having a plurality of pairs of AxB and AyB layers; and
an interface between each AxB layer and AyB layer; and
wherein;
at least one interface comprises;
at least one ramp change of a proportion of A; and
at least one step change of a proportion of A; and
A comprises at least one material;
B comprises at least one material; and
x≠
y.
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Specification