LCD device including a TFT for reducing leakage current

• US 20050041169A1
• Filed: 08/20/2004
• Published: 02/24/2005
• Est. Priority Date: 08/21/2003
• Status: Active Grant

• Current Assignee: HannStar Display Corporation
• Original Assignee: NEC LCD Technologies Limited (NEC Corporation)
• Inventors: Suzuki, Seiji, Kimura, Shigeru, Hashimoto, Yoshiaki
• Granted Patent: US 7,460,190 B2
• Time in Patent Office: Days
• US Class Current: 349/43
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence

Abstract

An amorphous-silicon TFT (thin-film-transistor) in an LCD device has a larger channel length at both the edge portions of the channel of the TFT compared to the central portion of the channel by forming chamfers at the corners of the source and drain electrodes. The larger channel length at both the edge portions reduces the leakage current caused by the turned-around light incident onto the channel.

Claims

1. A liquid crystal display (LCD) device comprising a TFT (thin-film-transistor) substrate mounting thereon a plurality of TFTS, a counter substrate mounting thereon a black matrix, a liquid crystal layer sandwiched between said TFT substrate and said counter substrate, and a backlight unit disposed at a rear side of said TFT substrate for irradiating said TFT substrate with backlight, each of said TFTs having a channel in a semiconductor layer, said channel having a channel length larger at an edge portion of said channel than at a central portion thereof.

2. The LCD device according to claim 1, wherein said channel length is larger at both edge portions of said channel than at said central portion thereof.

3. The LCD device according to claim 1, wherein said TFT includes a gate electrode disposed between said channel and said backlight unit, said gate electrode having a function of shielding said channel against said backlight.

4. The LCD device according to claim 1, wherein said semiconductor layer is made of an amorphous silicon film or a polysilicon film.

5. The LCD device according to claim 1, wherein said TFT includes source and drain electrodes opposing said gate electrode with an intervention of said semiconductor layer.

6. The LCD device according to claim 1, wherein said TFT includes an ohmic contact layer between said semiconductor layer and said source and drain electrodes.

7. The LCD device according to claim 1, wherein said source and drain electrodes of said TFT overlie said semiconductor layer.

8. A method for fabricating a TFT in an LCD device, comprising the steps of:

consecutively forming a gate electrode, a gate insulation film, a semiconductor layer and an ohmic contact layer of the TFT;

patterning said ohmic contact layer and said semiconductor layer;

forming a source electrode and a drain electrode of the TFT on said patterned ohmic contact layer; and

etching a portion of said patterned ohmic contact layer between said source electrode and said drain electrode by using said source electrode and said drain electrode as a mask to thereby expose a portion of said semiconductor layer as a channel, said channel having a channel length larger at an edge portion of said channel than at a central portion thereof.

9. A method for fabricating a TFT in an LCD device, comprising the steps of:

consecutively forming a gate electrode, a gate insulation film, a semiconductor layer and an ohmic contact layer of the TFT and a metallic film;

forming a photoresist film on said metallic film and exposing said photoresist film to exposure light having a specific wavelength through a photomask having a source electrode pattern, a drain electrode pattern and an intermediate pattern sandwiched between said source electrode pattern and said drain electrode pattern, said intermediate pattern having a width smaller than a limit of a resolution by said exposure light, to thereby form a photoresist mask pattern having a thickness larger at a region corresponding to said source and drain electrode patterns than at a region corresponding to a gap between said source electrode pattern and said drain electrode pattern;

patterning said metallic film, said ohmic contact layer and said semiconductor layer by using said photoresist mask pattern as a mask;

removing said photoresist mask pattern to leave a portion of said photoresist mask pattern having a specific thickness;

patterning said metallic film by using said portion of said photoresist mask pattern to form a source electrode and a drain electrode of the TFT; and

etching a portion of said patterned ohmic contact layer between said source electrode and said drain electrode by using said source electrode and said drain electrode as a mask to thereby expose a portion of said semiconductor layer as a channel, said channel having a channel length larger at an edge portion of said channel than at a central portion thereof.

10. The method according to claim 9, wherein said intermediate pattern is one or more slit pattern having said width smaller than said limit of resolution.

11. The method according to claim 9, wherein said intermediate pattern includes a plurality of stripe patterns arranged in an extending direction of said channel and each having dimensions smaller than said limit of resolution.

12. The method according to claim 9, wherein said intermediate pattern includes a plurality of dot patterns arranged in a matrix and having dimensions smaller than said limit of resolution.

13. The method according to claim 9, wherein said photoresist mask pattern removing step uses a reactive-ion-etching system.

14. The method according to claim 9, wherein said photoresist mask pattern removing step uses a UV ashing system.

15. The method according to claim 9, wherein said channel length is larger at both end portions of said channel than at said central portion thereof.

16. The method according to claim 9, wherein said semiconductor layer is made of an amorphous silicon film.