Floating gate memory cell, floating gate memory arrangement circuit arrangement and method for fabricating a floating gate memory cell

• US 20050048720A1
• Filed: 08/25/2004
• Published: 03/03/2005
• Est. Priority Date: 02/25/2002
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Specht, Michael, Hofmann, Franz, Graham, Andrew
• Granted Patent: US 7,385,243 B2
• Time in Patent Office: Days
• US Class Current: 438/264
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

Floating gate memory cell having a first layer with first and second source/drain regions and a channel region arranged between and next to the first and second source/drain regions, and a floating gate layer arranged on the first layer, wherein the first and second source/drain regions and the floating gate layer are formed of a metallically conductive material, and the channel region is formed of an electrically insulating material.

Claims

1. A floating gate memory cell, comprising:

a first layer having a first and second source/drain regions and a channel region arranged between and next to the first and second source/drain regions; and

a floating gate layer arranged on the first layer,

wherein the first and second source/drain regions and the floating gate layer are formed of a metallically conductive material, and the channel region is formed of an electrically insulating material.

2. The floating gate memory cell of claim 1, wherein the first and second source/drain regions and the floating gate layer include a metal.

3. The floating gate memory cell of claim 1, further comprising:

a first dielectric layer arranged between the first layer and the floating gate layer;

a second dielectric layer arranged on the floating gate layer; and

a control gate electrode layer arranged on the second dielectric layer.

4. The floating gate memory cell of claim 3, further comprising a substrate on which the first layer is arranged.

5. The floating gate memory cell of claim 4, wherein the substrate is made from an electrically insulating material.

6. The floating gate memory cell of claim 4 formed as a planar floating gate memory cell wherein electric current flows through the channel region parallel to the surface of the substrate.

7. The floating gate memory cell of claim 5, wherein the substrate is made from silicon dioxide.

8. The floating gate memory cell of claim 3, wherein, independently of one another, the first and second source/drain regions, the floating gate layer, and the control gate electrode layer include one or a combination of materials selected from the group consisting of aluminum, titanium, titanium nitride, copper, and tungsten.

9. The floating gate memory cell of claim 1, wherein the channel region includes one or a combination of the materials selected from the group consisting of tantalum oxide, titanium oxide, hafnium oxide, amorphous silicon, and zirconium oxide.

10. The floating gate memory cell of claim 3, wherein, independently of one another, the first dielectric layer and the second dielectric layer include one or a combination of the materials selected from the group consisting of aluminum oxide, silicon nitride, silicon dioxide, and lanthanum oxide.

11. The floating gate memory cell of claim 3, wherein the first and second source/drain regions are made from aluminum and the channel region is made from tantalum oxide, or wherein the first and second source/drain regions are made from titanium and the channel region is made from titanium oxide.

12. A floating gate memory arrangement having a plurality of floating gate memory cells as claimed in claim 1 arranged substantially in matrix form.

13. The floating gate memory arrangement of claim 12, wherein an area required for a floating gate memory cell is approximately 4 F², where F is a minimum feature size that is achieved in a context of a particular technology.

14. A circuit arrangement, comprising:

a circuit which is integrated in a semiconductor substrate and has at least one semiconductor component; and

at least one floating gate memory cell as claimed in claim 1 arranged on the integrated circuit.

15. A floating gate memory cell, comprising:

a substrate;

a layer sequence formed on the substrate and having a first source/drain region, a channel region arranged on the first source/drain region, and a second source/drain region arranged on the channel region, wherein the first and second source/drain regions are formed of a metallically conductive material, and the channel region is formed of an electrically insulating material;

a first dielectric layer arranged on the surface and side wall regions of the layer sequence and on a portion of the substrate surface that is devoid of the layer sequence;

a floating gate layer arranged on side wall regions of the first dielectric layer, wherein the floating gate layer is formed of a metallically conductive material;

a second dielectric layer arranged on uncovered surfaces of the first dielectric layer and on the floating gate layer; and

a control gate electrode layer arranged on the second dielectric layer,

wherein lateral edge sections of the first and second dielectric layers are arranged on the surface of the substrate.

16. The floating gate memory cell of claim 15, wherein the first and second source/drain regions and the floating gate layer include a metal.

17. The floating gate memory cell of claim 15, wherein the substrate is made from an electrically insulating material.

18. The floating gate memory cell of claim 16, wherein the substrate is made from silicon dioxide.

19. The floating gate memory cell of claim 15, wherein, independently of one another, the first and second source/drain regions, the floating gate layer, and the control gate electrode layer include one or a combination of materials selected from the group consisting of aluminum, titanium, titanium nitride, copper, and tungsten.

20. The floating gate memory cell of claim 15, wherein the channel region includes one or a combination of the materials selected from the group consisting of tantalum oxide, titanium oxide, hafnium oxide, amorphous silicon, and zirconium oxide.

21. The floating gate memory cell of claim 15, wherein, independently of one another, the first dielectric layer and the second dielectric layer include one or a combination of the materials selected from the group consisting of aluminum oxide, silicon nitride, silicon dioxide, and lanthanum oxide.

22. The floating gate memory cell of claim 15, wherein the first and second source/drain regions are made from aluminum and the channel region is made from tantalum oxide, or wherein the first and second source/drain regions are made from titanium and the channel region is made from titanium oxide.

23. The floating gate memory cell of claim 15 configured as a vertical transistor arrangement, wherein electric current between the first and second source/drain regions through the channel region flows in an orthogonal direction with respect to the surface of the substrate.

24. A floating gate memory arrangement having a plurality of floating gate memory cells as claimed in claim 15 arranged substantially in matrix form.

25. The floating gate memory arrangement of claim 24, wherein an area required for a floating gate memory cell is approximately 4 F², where F is a minimum feature size that is achieved in a context of a particular technology.

26. A circuit arrangement, comprising:

a circuit having at least one semiconductor component; and

at least one floating gate memory cell as claimed in claim 15 on the integrated circuit.

27. A method of fabricating a floating gate memory cell, comprising the steps of:

forming a first layer having first and second source/drain regions and a channel region arranged between and next to the first and second source/drain regions; and

forming a floating gate layer on the first layer,

wherein the first and second source/drain regions and the floating gate layer are formed of a metallically conductive material, and the channel region is formed of an electrically insulating material.

28. The method of claim 27, further comprising the steps of:

forming a first dielectric layer between the first layer and the floating gate layer;

forming a second dielectric layer on the floating gate layer; and

forming a control gate electrode layer on the second dielectric layer.

29. A method of fabricating a floating gate memory cell, comprising the steps of:

providing a substrate;

forming a layer sequence on the substrate, the layer sequence having first source/drain layer, a channel layer arranged on the first source/drain layer, and a second source/drain layer arranged on the channel layer, wherein the first and second source/drain layers are formed of a metallically conductive material, and the channel layer is formed of an electrically insulating material;

patterning the layer sequence laterally using a lithography process and an etching process so that a first source/drain region is formed from the first source/drain layer, a channel region is formed from the channel layer, and a second source/drain region is formed from the second source/drain layer;

forming a first dielectric layer on the surface and side wall regions of the layer sequence and on a portion of the substrate surface that is devoid of the layer sequence;

forming a floating gate layer at least partially on side wall regions of the first dielectric layer, wherein the floating gate layer is formed of a metallically conductive material;

forming a second dielectric layer on at least a partial region of on an uncovered surface of the first dielectric layer and on the floating gate layer; and

forming a control gate electrode layer (241) on the second dielectric layer,

wherein lateral edge sections of the first and second dielectric layers are formed on the surface of the substrate.