Mechanisms for assuring quality of service for programs executing on a multithreaded processor
First Claim
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1. A mechanism for assuring quality of service for a context in a digital processor, comprising:
- a first scheduling register dedicated to the context and having N out of M bits set; and
a first scheduler that consults the register to assign issue slots to the context;
wherein the first scheduler grants issue slots for the context by referencing the N bits in the first register, and repeats a pattern of assignments of issue slots after referencing the M bits of the first register.
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Abstract
A mechanism for assuring quality of service for a context in a digital processor has a first scheduling register dedicated to the context, the register having N out of M bits set, and a first scheduler that consults the register to assign issue slots to the context. The first scheduler grants issue slots for the context by referencing the N bits in the first register, and repeats a pattern of assignments of issue slots after referencing the M bits of the first register.
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Citations
38 Claims
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1. A mechanism for assuring quality of service for a context in a digital processor, comprising:
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a first scheduling register dedicated to the context and having N out of M bits set; and
a first scheduler that consults the register to assign issue slots to the context;
wherein the first scheduler grants issue slots for the context by referencing the N bits in the first register, and repeats a pattern of assignments of issue slots after referencing the M bits of the first register. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for assuring quality of service for a context in a digital processor, comprising the steps of:
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(a) assigning a register as a scheduling register to the context, the register having M bits;
(b) setting N bits of the register in a pattern desired for issuing instructions for the context; and
(c) accessing the pattern of bits sequentially, assigning an issue slot to the context according to whether a bit is set or not set, and repeating after reaching the end of the pattern. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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- 17. A digital processor for supporting and executing multiple contexts, comprising one or more specific scheduling registers dedicated one-to-one with specific ones of the contexts, and having M bits set in a specific pattern for a scheduler to access bit-by-bit sequentially to grant issue slots to the contexts.
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25. A processing system for assuring quality of service for a context, comprising:
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at least one processor;
a scheduling register accessible to the processor, dedicated to the context and having M bits set in a pattern; and
a scheduler that consults the register to assign issue slots to the context;
wherein the scheduler schedules issue slots sequentially for the context associated with the register by accessing the pattern of bits in the register sequentially, and repeating when reaching the end of the pattern. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32)
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- 33. A digital storage medium having written thereon a software program code set executable on a digital processor, the code set comprising function code for reading sequentially bits of a register dedicated to a specific context and assigning issue slots to the associated specific context according to whether each bit is set or not set.
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37. A computer-readable medium to direct the operations of a computer, comprising:
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computer-readable program code for describing a mechanism for assuring quality of service for a context in a digital processor, the program code including;
a first program code segment for describing a scheduling register dedicated to the context and having N out of M bits set; and
a second program code segment for describing a scheduler that consults the register to assign issue slots to the context;
wherein the scheduler grants issue slots for the context by referencing the N bits in the first register, and repeats a pattern of assignments of issue slots after referencing the M bits of the register.
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38. A computer data signal embodied in a transmission medium comprising:
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computer-readable program code for describing a processing system for assuring quality of service for a context, the program code including;
a first program code segment for describing at least one processor;
a second program code segment for describing a scheduling register accessible to the processor, dedicated to the context and having M bits set in a pattern; and
a third program code segment for describing a scheduler that consults the register to assign issue slots to the context;
wherein the scheduler schedules issue slots sequentially for the context associated with the register by accessing the pattern of bits in the register sequentially, and repeating when reaching the end of the pattern.
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Specification