Video encoding using parallel processors

• US 20050053131A1
• Filed: 07/13/2004
• Published: 03/10/2005
• Est. Priority Date: 07/14/2003
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Hung, Ching-Yu, Talla, Deependra, Domke, Damon, Yoo, Youngjun
• Granted Patent: US 7,593,580 B2
• Time in Patent Office: Days
• US Class Current: 375/240.10
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/436 using parallelised computational arrangements

Abstract

A digital video acquisition system including a plurality of image processors (30A; 30B) is disclosed. A CCD imager (22) presents video image data on a bus (video_in) in the form of digital video data, arranged in a sequence of frames. A master image processor (30A) captures and encodes a first group of frames, and instructs a slave image processor (30B) to capture and encode a second group of frames presented by the CCD imager (22) before the encoding of the first group of frames is completed by the master image processor. The master image processor (30A) completes its encoding, and is then available to capture and encode another group of frames in the sequence. Video frames that are encoded by the slave image processor (30B) are transferred to the master image processor (30A), which sequences and stores the transferred encoded frames and also those frames that it encodes in a memory (36A; 38). The parameters of the encoding operation can be dynamically adjusted, for example in response to the nature of the video sequences being captured.

Claims

1. A digital video acquisition system, comprising:

an imager for generating a sequence of digital video frame data;

a master image processor, having an input coupled to receive the digital video frame data from the imager, for encoding the digital video frame data into a compressed format;

a master memory, coupled to the master image processor, for storing encoded digital video data;

a first slave image processor, having an input coupled to receive the digital video frame data from the imager, having a control input for receiving control signals from the master image processor, the first slave image processor for encoding the digital video frame data into a compressed format when enabled by the master image processor.

2. The system of claim 1 wherein the master image processor controls the first slave image processor so that the master image processor encodes digital video frame data corresponding to a first group of pictures, and so that the slave image processor encodes digital video frame data corresponding to a second group of pictures contiguous in the sequence with the first group of pictures.

3. The system of claim 2, wherein the master image processor completes encoding the digital video frame data corresponding to the first group of pictures while the slave image processor is encoding the digital video frame data corresponding to the second group of pictures.

4. The system of claim 1, further comprising:

an audio codec, for generating a sequence of digital audio data corresponding to the sequence of digital video data, the audio codec having an output coupled to the master image processor.

5. The system of claim 4, wherein the master image processor is also for storing digital audio data in the master memory in association with the encoded digital video data.

6. The system of claim 1, further comprising:

a first Slave memory, coupled to the first slave image processor, for storing digital video data encoded by the first slave image processor.

7. The system of claim 6, further comprising:

a bus connected to the master image processor and the first slave image processor;

wherein the first slave image processor is also for transferring encoded digital video data to the master image processor over the bus;

and wherein the master image processor is also for storing encoded digital video data received from the first slave image processor over the bus in the master memory.

8. The system of claim 1, wherein the master memory comprises:

random access memory.

9. The system of claim 8, wherein the master memory further comprises:

a memory card.

10. The system of claim 1, further comprising:

a display, coupled to the master image processor, for displaying video image data from the master image processor.

11. The system of claim 1, further comprising:

a second slave image processor, having an input coupled to receive the digital video frame data from the imager, having a control input for receiving control signals from the master image processor, the second slave image processor for encoding the digital video frame data into a compressed format when enabled by the master image processor.

12. A method of encoding digital video image data, comprising the steps of:

receiving a sequence of digital video image data;

encoding a first group of frames of the sequence with a master image processor;

encoding a second group of frames of the sequence with a slave image processor during the step of encoding the first group of frames with the master image processor; and

storing the encoded first and second group of frames in a memory.

13. The method of claim 12, further comprising:

encoding a third group of frames with the master image processor during the step of encoding the second group of frames.

14. The method of claim 12, further comprising:

after the step of encoding the second group of frames, communicating the encoded second group of frames to the master image processor;

wherein the storing step is performed by the master image processor.

15. The method of claim 12, further comprising:

selecting the number of frames in each group of frames.

16. The method of claim 15, further comprising:

after the encoding of one of the plurality of groups of frames, changing the number of frames each group of frames.

17. The method of claim 12, further comprising:

prior to the receiving step, booting the master image processor from a boot memory;

during the booting step, maintaining the slave image processor in a reset state; and

then booting the first slave image processor from the boot memory.

18. The method of claim 12, further comprising:

during the encoding steps, displaying video images corresponding to the received sequence of digital video image data.

19. The method of claim 12, further comprising:

during the receiving of the first group of frames, issuing a control signal from the master image processor to the slave image processor, the control signal indicating that the slave image processor is to begin encoding a selected number of frames corresponding to the second group of frames.

20. The method of claim 19, further comprising:

responsive to the control signal, issuing an acknowledge from the slave image processor to the master image processor.

21. The method of claim 20, further comprising:

setting an encode counter in the slave image processor with the selected number of frames; and

responsive to the acknowledge, setting a do-not-encode counter in the master image processor with the selected number of frames.