Ternary and higher multi-value digital scramblers/descramblers
First Claim
1. A method of scrambling a ternary signal with a scrambler, the ternary signal being able to assume on of three states and the scrambler having a first scrambling ternary logic device that implements a ternary logic function, sc, and a scrambling logic circuit, comprising;
- inputting the ternary signal and an output from the scrambling logic circuit to the first scrambling ternary logic device;
inputting an output from the first scrambling ternary logic device to the scrambling logic circuit;
wherein the ternary logic function, sc, satisfies the following equations;
(1) A sc B=C, where A is the ternary signal, B is the output from the scrambling logic circuit and C is the output from the first scrambling ternary logic device;
(2) C sc B=A, if C and B were input to the first scrambling ternary logic device; and
(3) A sc C=B;
if A and C were input to the first scrambling ternary logic device; and
whereby the output from the first scrambling ternary logic device is a scrambled version of the ternary signal.
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Accused Products
Abstract
Ternary (3-value) and higher, multi-value digital scramblers/descramblers in digital communications. The method and apparatus of the present invention includes the creation of ternary (3-value) and higher value truth tables that establish ternary and higher value scrambling functions which are its own descrambling functions. The invention directly codes by scrambling ternary and higher-value digital signals and directly decodes by descrambling with the same function. A disclosed application of the invention is the creation of composite ternary and higher-value scrambling devices and methods consisting of single scrambling devices or functions combined with ternary or higher value shift registers. Another disclosed application is the creation of ternary and higher-value spread spectrum digital signals. Another disclosed application is a composite ternary or higher value scrambling system, comprising an odd number of scrambling functions and the ability to be its own descrambler.
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Citations
46 Claims
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1. A method of scrambling a ternary signal with a scrambler, the ternary signal being able to assume on of three states and the scrambler having a first scrambling ternary logic device that implements a ternary logic function, sc, and a scrambling logic circuit, comprising;
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inputting the ternary signal and an output from the scrambling logic circuit to the first scrambling ternary logic device;
inputting an output from the first scrambling ternary logic device to the scrambling logic circuit;
wherein the ternary logic function, sc, satisfies the following equations;
(1) A sc B=C, where A is the ternary signal, B is the output from the scrambling logic circuit and C is the output from the first scrambling ternary logic device;
(2) C sc B=A, if C and B were input to the first scrambling ternary logic device; and
(3) A sc C=B;
if A and C were input to the first scrambling ternary logic device; and
whereby the output from the first scrambling ternary logic device is a scrambled version of the ternary signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. Apparatus for scrambling a ternary signal that can assume one of three states, comprising:
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a first scrambling ternary logic device that implements a ternary logic function, sc, the first scrambling ternary logic device having a first and second input and an output;
a scrambling logic circuit having an input and an output;
wherein the ternary signal is input to the first input of the first scrambling ternary logic device, the output of the scrambling logic circuit is input to the second input of the first scrambling ternary logic device and the output of the first scrambling ternary logic devices is provided to the input of the scrambling logic circuit, the ternary logic function, sc, satisfying the following equations;
(1) A sc B=C, where A is the ternary signal, B is the output from the scrambling logic circuit and C is the output from the first scrambling ternary logic device;
(2) C sc B=A, if C and B were input to the first scrambling ternary logic device; and
(3) A sc C=B;
if A and C were input to the first scrambling ternary logic device; and
whereby a scrambled ternary signal is provided on the output of the first scrambling ternary logic device. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A method of scrambling a multi-value signal that can assume one of x states, wherein x is greater than or equal to 4, with a scrambler, the scrambler having a first scrambling multi-value logic device that implements a multi-value logic function, fc, and a scrambling logic circuit, comprising:
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inputting the multi-value signal and an output from the scrambling logic circuit to the first scrambling multi-value logic device;
inputting an output from the first scrambling multi-value logic device to an input to the scrambling logic circuit;
wherein the multi-value logic function, fc, satisfies the following equations;
(1) A fc B=C, where A is the multi-value signal, B is the output from the scrambling logic circuit and C is the output from the first scrambling multi-value logic device;
(2) C fc B=A, if C and B were input to the first scrambling multi-value logic device; and
(3) A fc C=B;
if A and C were input to the first scrambling multi-value logic device; and
whereby the output from the first scrambling multi-value logic device is a scrambled version of the multi-value signal. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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35. Apparatus for scrambling a multi-value signal that can assume one of x states, wherein x is greater than or equal to 4, comprising:
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a first scrambling multi-value logic device that implements a multi-value logic function, fc, the first multi-value logic device having a first and second input and an output;
a scrambling logic circuit having an input and an output;
wherein the multi-value signal is input to the first input of the first scrambling multi-value logic device, the output of the scrambling logic circuit is input to the second input of the first scrambling multi-value logic device and the output of the first scrambling multi-value logic device is input to the input of the scrambling logic circuit, the multi-value logic function, sc, satisfying the following equations;
(1) A fc B=C, where A is the multi-value signal, B is the output from the scrambling logic circuit and C is the output from the first scrambling multi-value logic device;
(2) C fc B=A, if C and B were input to the first scrambling multi-value logic device; and
(3) A fc C=B;
if A and C were input to the first scrambling multi-value logic device; and
whereby a scrambled multi-value signal is provided on the output of the first scrambling multi-value logic device. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46)
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Specification