Semiconductor device and method for fabricating the same

• US 20050054195A1
• Filed: 07/28/2004
• Published: 03/10/2005
• Est. Priority Date: 09/09/2003
• Status: Active Grant

• Current Assignee: Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Umimoto, Hiroyuki, Ueda, Tetsuya, Handa, Takato
• Granted Patent: US 7,265,450 B2
• Time in Patent Office: Days
• US Class Current: 438/638
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76865 Selective removal of parts of the layer H01L21/76844 takes precedence
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76886 Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An inventive semiconductor device includes: a lower interlayer dielectric film provided on a substrate; a lower interconnect made up of a lower barrier metal layer formed along a wall surface of a lower interconnect groove in the lower interlayer dielectric film, and a copper film; and an upper plug and an upper interconnect. The upper plug passes through a silicon nitride film and comes into contact with the copper film of the lower interconnect. The lower interconnect is provided with a large number of convex portions buried in concave portions of the lower interconnect groove. Thus, voids in the lower interconnect are also gettered by the convex portions. Accordingly, the concentration of voids in the contact area between the lower interconnect and the upper plug is relieved, and an increase in contact resistance is suppressed.

Claims

1. A semiconductor device comprising:

a substrate provided with a semiconductor element;

a lower interlayer dielectric film provided on the substrate;

a lower interconnect groove provided in the lower interlayer dielectric film;

a lower interconnect provided within the lower interconnect groove and having convex or concave portions at least at one of its side surfaces, bottom surface and upper surface;

an upper interlayer dielectric film provided over the lower interlayer dielectric film and the lower interconnect; and

an upper plug that passes through the upper interlayer dielectric film and comes into contact with a part of the lower interconnect.

2. The semiconductor device according to claim 1,

wherein the lower interconnect groove is provided at its bottom surface with concave or convex portions, and

wherein the convex or concave portions of the lower interconnect have shapes corresponding to those of the concave or convex portions of the lower interconnect groove.

3. The semiconductor device according to claim 1,

wherein the lower interconnect groove is provided at its side surfaces with concave or convex portions, and

wherein the convex or concave portions of the lower interconnect have shapes corresponding to those of the concave or convex portions of the lower interconnect groove.

4. The semiconductor device according to claim 1,

wherein the lower interconnect groove is provided at its wall surface with concave and convex portions having irregular shapes, and

wherein the convex portions of the lower interconnect have shapes corresponding to those of the concave portions of the concave and convex portions of the lower interconnect groove.

5. The semiconductor device according to claim 1,

wherein the lower interconnect includes a portion formed by a copper film.

6. A semiconductor device comprising:

a substrate provided with a semiconductor element;

a lower interlayer dielectric film provided on the substrate;

a lower interconnect groove provided in the lower interlayer dielectric film;

a lower interconnect provided within the lower interconnect groove;

a stress-relieving conductor film for covering an upper surface of the lower interconnect;

an upper interlayer dielectric film provided on the stress-relieving conductor film; and

an upper plug that passes through the upper interlayer dielectric film and comes into contact with a part of the stress-relieving conductor film.

7. The semiconductor device according to claim 6,

wherein the stress-relieving conductor film is a TaN film.

8. A semiconductor device comprising:

a substrate provided with a semiconductor element;

a lower interlayer dielectric film provided on the substrate;

a lower interconnect groove provided in the lower interlayer dielectric film;

a lower interconnect that is provided within the lower interconnect groove and that has a dopant-containing conductor film into which dopant ions are implanted;

an upper interlayer dielectric film provided over the lower interconnect and the lower interlayer dielectric film; and

an upper plug that passes through the upper interlayer dielectric film and comes into contact with a part of the lower interconnect.

9. The semiconductor device according to claim 8,

wherein the dopant-containing conductor film is a Si-containing copper film.

10. A method for fabricating a semiconductor device, the method comprising the steps of

a) forming a lower interlayer dielectric film on a substrate provided with a semiconductor element;

b) forming, in the lower interlayer dielectric film, a lower interconnect groove having concave or convex portions at its bottom surface;

c) filling the lower interconnect groove with a conductor material, thereby forming a lower interconnect with convex or concave portions having shapes corresponding to those of the concave or convex portions of the lower interconnect groove;

d) forming an upper interlayer dielectric film over the lower interlayer dielectric film and the lower interconnect; and

e) forming an upper plug that passes through the upper interlayer dielectric film and comes into contact with a part of the lower interconnect.

11. The method according to claim 10,

wherein the step b) comprises the steps of:

forming, in the lower interlayer dielectric film, bottom and side surfaces of the lower interconnect groove; and

etching the lower interlayer dielectric film using an etching mask having openings on the bottom surface of the lower interconnect groove, thereby forming the concave portions in regions of the bottom surface of the lower interconnect groove which are exposed to the openings.

12. The method according to claim 10 or 11,

wherein in the step a), a first layer and a second layer are sequentially deposited as the lower interlayer dielectric film, the second layer being made of an insulating material having an etch rate different from that of the first layer,

wherein in the step b), the second layer is exposed to side surfaces of the lower interconnect groove, and

wherein in the step b), side surfaces of the lower interlayer dielectric film are etched, thereby forming the concave or convex portions in regions of the side surfaces of the lower interconnect groove where the second layer is exposed.

13. The method according to claim 10,

wherein the step b) comprises the steps of:

forming, in the lower interlayer dielectric film, bottom and side surfaces of the lower interconnect groove by performing etching such that a deposition film remains on the bottom and side surfaces of the lower interconnect groove; and

etching portions of the lower interlayer dielectric film exposed to the lower interconnect groove, with the deposition film remaining on the bottom and side surfaces of the lower interconnect groove, thus forming irregular-shaped concave and convex portions at the bottom and side surfaces of the lower interconnect groove.

14. A method for fabricating a semiconductor device, the method comprising the steps of:

a) forming a lower interlayer dielectric film on a substrate provided with a semiconductor element;

b) forming a lower interconnect groove in the lower interlayer dielectric film;

c) filling the lower interconnect groove with a conductor material, thereby forming a lower interconnect;

d) forming a stress-relieving conductor film for covering a surface of the lower interconnect;

e) forming an upper interlayer dielectric film on the lower interlayer dielectric film and the stress-relieving conductor film; and

f) forming an upper plug that passes through the upper interlayer dielectric film and comes into contact with a part of the stress-relieving conductor film.

15. The method according to claim 14,

wherein the stress-relieving conductor film is a TaN film.

16. A method for fabricating a semiconductor device, the method comprising the steps of:

a) forming a lower interlayer dielectric film on a substrate provided with a semiconductor element;

b) forming a lower interconnect groove in the lower interlayer dielectric film;

c) filling the lower interconnect groove with a conductor material, thereby forming a lower interconnect;

d) implanting dopant ions into the lower interconnect;

e) forming an upper interlayer dielectric film over the lower interlayer dielectric film and the lower interconnect, after the step d) has been performed; and

f) forming an upper plug that passes through the upper interlayer dielectric film and comes into contact with a part of the lower interconnect.

17. The method according to claim 16,

wherein in the step c), the lower interconnect groove is filled with a copper film as the conductor material, thereby forming the lower interconnect, and

wherein in the step d), Si ions are implanted into the lower interconnect.