Serial asynchronous interface with slip coding/decoding and CRC checking in the transmission and reception paths

• US 20050058188A1
• Filed: 08/03/2004
• Published: 03/17/2005
• Est. Priority Date: 08/06/2003
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Lorenz, Rudiger
• Granted Patent: US 7,607,064 B2
• Time in Patent Office: Days
• US Class Current: 375/219
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0061 Error detection codes
• CPC Class Codes: H04L 2001/0094 Bus

Abstract

A transmitting/receiving unit for asynchronous data transmission has a CRC unit and a transmission FIFO in a transmission path. A coding unit for SLIP-coding of data to be transmitted can optionally be connected in the transmission path. Furthermore, a CRC unit and a reception FIFO are arranged in the reception path of the module. A decoding unit for SLIP-decoding of received data can optionally be connected in the reception path. The unit is connected to a data bus, in which case a DMA unit can also be connected to the data bus.

Claims

1. A transmitting/receiving unit for asynchronous data transmission, comprising:

a coding unit and a decoding unit for coding of data to be transmitted and for decoding of received data, respectively, wherein the coding unit and the decoding unit are selectively arranged in a transmission path and in a reception path, respectively, and

first and second error identification and error correction units operable to identify and correct errors of data to be transmitted and received data in the transmission and reception paths, respectively.

2. The transmitting/receiving unit of claim 1, wherein the coding unit is selectively connected in the transmission path as a function of a coding requirement of data to be transmitted, and the decoding unit is selectively connected in the reception path as a function of a decoding requirement of received data.

3. The transmitting/receiving unit of claim 2, wherein the coding unit is connected downstream from the first error identification and error correction unit in the transmission path if coding of data to be transmitted is required, and the decoding unit is connected upstream of the second error identification and error correction unit in the reception path if decoding of received data is required.

4. The transmitting/receiving unit of claim 1, wherein the first error identification and error correction unit in the transmission path is electrically coupled to a transmission storage register, and the coding unit is coupled in the transmission path between the first error identification and error correction unit and a transmission storage register if coding of data to be transmitted is to be performed.

5. The transmitting/receiving unit of claim 4, wherein the second error identification and error correction unit in the reception path is electrically coupled to a reception storage register, and the decoding unit is connected in the reception path between the second error identification and error correction unit and the reception storage register if decoding of received data is to be performed.

6. The transmitting/receiving unit of claim 5, wherein the transmission storage register in the transmission path and the reception storage register in the reception path are electrically connected to a monitoring unit configured to check communication protocols, wherein the monitoring unit is arranged in the transmitting/receiving module.

7. The transmitting/receiving unit of claim 1, wherein the coding unit and the decoding unit are respectively designed for SLIP coding and decoding.

8. The transmitting/receiving unit of claim 1, wherein the first and second error identification and error correction units comprise cyclic redundancy check (CRC) units.

9. The transmitting/receiving unit of claim 1, wherein the first and second error identification and error correction units are configured to be connected to a data bus line external to the transmitting/receiving unit.

10. The transmitting/receiving unit of claim 1, in combination with a DMA unit electrically connected to a data bus line, wherein the DMA unit is operably coupled to the first and second error identification and error correction units in the transmitting/receiving unit via the data bus line.

11. A transceiver, comprising:

a reception storage register configured to store received data therein;

a received data error identification and correction unit configured to identify and correct errors associated with the received data;

a decoding unit selectively coupled between the reception storage register and the received data error identification and correction unit, and configured to decode received data from the reception storage register if the received data is coded, wherein the reception storage register, the received data error identification and correction unit and the decoding unit comprise a reception path of the transceiver;

a transmission storage register;

a transmission data error identification and correction unit configured to identify and correct errors associated with data to be transmitted; and

a coding unit selectively coupled between the transmission storage register and the transmission data error identification and correction unit, and configured to code data to be transmitted from the transmission data error and correction unit if the data to be transmitted is to be coded, wherein the transmission data error and correction unit, the transmission storage register, and the transmission data error identification and correction unit comprise a transmission path of the transceiver.

12. The transceiver of claim 11, further comprising a monitoring unit coupled to the reception storage register and the transmission storage register, and configured to check communication protocols and facilitate reception of data to the transceiver and transmission of data from the transceiver, respectively.

13. The transceiver of claim 11, wherein the reception storage register and the transmission storage register each comprise a first-in, first-out memory (FIFO).

14. A method of asynchronous data transmission, comprising:

receiving data and storing such received data in a reception storage register within a transceiver device;

selectively decoding the received data if the received data is coded data within the transceiver device;

receiving the decoded data or the data from the reception storage register, and performing an error identification and correction of the received data within the transceiver device;

performing an error identification and correction of data to be transmitted within the transceiver device;

selectively coding the data to be transmitted after the error identification and correction thereof if the data to be transmitted is to be coded within the transceiver device; and

storing the data to be transmitted in a transmission storage register within the transceiver device after the selective coding thereof.

15. The method of claim 14, wherein the received data is automatically decoded upon a reading of the reception storage register (ESR) and, if required, error identification and error correction are carried out automatically after the decoding.

16. The method of claim 14, wherein the data to be transmitted is automatically analyzed and errors identified and corrected automatically, if required, and coded automatically, if required, prior to be written to the transmission storage register.

17. The method of claim 14, wherein the data to be transmitted and the received data are respectively SLIP-coded and SLIP-decoded.

18. The method of claim 17, further comprising storing at least two bytes in the reception storage register, and using the at least two bytes for SLIP decoding of received SLIP coded data bytes in the reception storage register.

19. The method of claim 14, wherein the error identification and the error correction for received data and data to be transmitted comprises identifying and correcting errors using a cyclic redundancy check (CRC) algorithm.