Pipeline processing system and information processing apparatus

• US 20050058438A1
• Filed: 07/30/2004
• Published: 03/17/2005
• Est. Priority Date: 07/31/2003
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Hayashi, Tsuneo
• Granted Patent: US 7,539,859 B2
• Time in Patent Office: Days
• US Class Current: 386/231
• CPC Class Codes: G11B 20/00086 Circuits for prevention of unauthorised reproduction or copying, e.g. piracy indicating unauthorised use of record carriers in general G11B23/28; scrambling for television signal recording H04N5/913; network architectures or network protocols for network security H04L63/00; cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
• CPC Class Codes: H04N 5/85 on discs or drums

Abstract

A pipeline processing system and an information processing apparatus not malfunctioning even if there is a pipeline stage in which data is not correctly written, including a plurality of processing circuits for applying predetermined processing to a plurality of data blocks; memories accessed by any circuit of a plurality of processing circuits, encryptor for encrypting the data based on key information set for each series of pipeline processings continuously processed when storing processing results of the circuits in the memories; and decoders for decoding data based on set information used for the encrypting when reading the data encrypted and stored in the memories.

Claims

1. A pipeline processing system applying pipeline processing for a plurality of data, comprising:

a plurality of processing circuits configuring pipeline stages and applying predetermined processings to said plurality of data;

a memory portion including at least one memory able to store data having a magnitude required in at least one pipeline stage and accessed by any processing circuit of said plurality of processing circuits; and

an encrypting circuit for encrypting data based on information set for each series of pipeline processing to be continuously processed when the processing results of said processing circuits are stored in the memories of said memory portion.

2. A pipeline processing system as set forth in claim 1, further comprising a decoding circuit for decoding data based on set information used for the encrypting when reading out the data encrypted and stored in said memories to a desired processing circuit.

3. A pipeline processing system as set forth in claim 1, further comprising a bus portion for switching data paths between said plurality of processing circuits and memories of said memory portion in accordance with predetermined status information and transferring data between pipeline stages.

4. A pipeline processing system as set forth in claim 3, wherein said bus portion switches said data paths in accordance with status information transitioning according to the state of processing of at least one processing circuit among said plurality of processing circuits.

5. A pipeline processing system as set forth in claim 1, further comprising a circuit for outputting stored data from a memory storing data after pipeline processing in accordance with a request of the system.

6. A pipeline processing system as set forth in claim 1, further comprising a circuit for storing data before the start of pipeline processing in a predetermined memory of said memory portion in accordance with a request to the system.

7. A pipeline processing system as set forth in claim 1, further comprising a circuit for outputting stored data from a memory storing data after pipeline processing in accordance with a request of the system and storing the data before the start of pipeline processing in a predetermined memory of said memory portion in accordance with a request to the system.

8. An information processing apparatus for reading recorded data from a medium recording data of a predetermined format, comprising:

a demodulation circuit for configuring a pipeline stage and demodulating said read data;

an error processing circuit configuring a pipeline stage and performing predetermined error processing with respect to the data after said demodulation;

a memory portion including at least one memory able to store data having a magnitude required in at least one pipeline stage and accessed by any circuit of said demodulation circuit or the error processing circuit; and

an encrypting circuit for encrypting data based on information set for each series of pipeline processing to be continuously processed when the processing results of said demodulation circuit and error processing circuit are stored in the memories of said memory portion.

9. An information processing apparatus as set forth in claim 8, further comprising a decoding circuit for decoding data based on set information used for the encrypting when reading out the data encrypted and stored in said memories to a desired circuit

10. An information processing apparatus as set forth in claim 8, further comprising a bus portion for switching data paths between said demodulation circuit and error processing circuit and memories of said memory portion in accordance with predetermined status information transitioning in accordance with the state of processing of at least one circuit among said demodulation circuit and error processing circuit and transferring data between pipeline stages.

11. An information processing apparatus as set forth in claim 10, wherein said bus portion switches said data paths in accordance with status information transitioning according to the state of processing of at least one circuit among said demodulation circuit and error processing circuit and transfers data between pipeline states.

12. An information processing apparatus as set forth in claim 8, further comprising an interface circuit for outputting stored data from a memory storing data after pipeline processing in accordance with a request of the system.

13. An information processing apparatus for recording input data as the data of a predetermined format into the media, comprising:

a recording data preparation circuit for preparing the data to be recorded based on said each input data;

a modulation circuit configuring a pipeline stage, modulating said prepared recording data, and outputting the same as the recording data to said medium;

a memory portion including at least one memory able to store the data having a magnitude required in at least each pipeline stage and accessed by any circuit of said modulation circuit or recording data preparation circuit; and

an encrypting circuit for encrypting the data based on the information set for each of a series of pipeline processings continuously processed when the processing results of said recording data preparation circuit are stored in the memories of said memory portion.

14. An information processing apparatus as set forth in claim 13, further comprising a decoding circuit for decoding data based on set information used for the encrypting when reading out the data encrypted and stored in said memories to said modulation circuit or recording data preparation circuit.

15. An information processing apparatus as set forth in claim 13, further comprising a bus portion for switching data paths between said demodulation circuit and recording data preparation circuit and a plurality of memories of said memory portion in accordance with predetermined status information and transferring data between pipeline stages.

16. An information processing apparatus as set forth in claim 15, wherein said bus portion switches said data paths in accordance with status information transitioning according to the state of processing of at least one circuit among said demodulation circuit and recording data preparation circuit.

17. An information processing apparatus as set forth in claim 13, further comprising an interface circuit for storing data before the start of pipeline processing to a predetermined memory of said memory portion in accordance with a request of the system.

18. An information processing apparatus for reading recorded data from a medium recording data of a predetermined format and recording input data as data of a predetermined format into the medium, comprising:

a demodulation circuit configuring a pipeline stage and demodulating each read data;

an error processing circuit configuring a pipeline stage and performing predetermined error processing with respect to said data after demodulation;

a recording data preparation circuit configuring a pipeline stage and preparing data to be recorded based on each input data;

a modulation circuit configuring a pipeline stage, modulating said prepared recording data, and outputting the same as the recording data to said medium;

a memory portion including at least one memory able to store data having a magnitude required in at least each pipeline stage and accessed by any circuit of said demodulation circuit, error processing circuit, recording data preparation circuit, and modulation circuit; and

an encrypting circuit for encrypting data based on information set for each series of pipeline processings continuously processed when the processing results of said demodulation circuit, error processing circuit, and recording data preparation circuit are stored in the memories of said memory portion.

19. An information processing apparatus as set forth in claim 18, further comprising a decoding circuit for decoding data based on set information used for the encrypting when reading out the data encrypted and stored in said memories to said modulation circuit or recording data preparation circuit.

20. An information processing apparatus as set forth in claim 18, further comprising a bus portion for switching data paths between said demodulation circuit and error processing circuit or said recording data preparation circuit and modulation circuit and a plurality of memories of said memory portion in accordance with predetermined status information and transferring data between pipeline stages.

21. An information processing apparatus as set forth in claim 20, wherein said bus portion switches said data paths in accordance with status information transitioning according to the state of processing of at least one circuit among said demodulation circuit and error processing circuit or said recording data preparation circuit and modulation circuit.

22. An information processing apparatus as set forth in claim 20, further comprising an interface circuit for outputting stored data from a memory storing data after pipeline processing in accordance with a request of the system and storing data before the start of pipeline processing in a predetermined memory of said memory portion in accordance with a request to the system.