Light emitting device processes

• US 20050059179A1
• Filed: 07/22/2004
• Published: 03/17/2005
• Est. Priority Date: 09/17/2003
• Status: Active Grant

• Current Assignee: Formosa Epitaxy Incorporated (Epistar Corporation)
• Original Assignee: Luminus Devices Incorporated (Sanan Optoelectronics Company Limited)
• Inventors: Lim, Michael, Erchak, Alexei A., Graff, John, Duncan, Scott, Minsky, Milan, Weig, Matthew
• Granted Patent: US 7,344,903 B2
• Time in Patent Office: Days
• US Class Current: 438/22
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate

Abstract

Light-emitting devices, and related components, processes, systems and methods are disclosed.

Claims

1. A method comprising:

providing a multilayer stack including a substrate, a semiconductor layer, and a quantum well containing region;

etching at least a portion of the quantum well containing region to provide an etched multilayer stack including a plurality of mesas supported by the substrate;

bonding the etched multilayer stack to a submount; and

removing the substrate.

2. The method of claim 1, further comprising forming at least one light emitting device from at least one of the mesas.

3. The method of claim 2, wherein the light emitting device is a light emitting diode.

4. The method of claim 3, wherein the light emitting diode is a photonic lattice light emitting diode.

5. The method of claim 1, wherein removing the substrate includes exposing the semiconductor layer to electromagnetic radiation to partially decompose the semiconductor layer.

6. The method of claim 5, wherein the electromagnetic radiation exposes a portion of the mesa.

7. The method of claim 5, wherein the electromagnetic radiation overlaps an edge of the mesa.

8. The method of claim 7, wherein the electromagnetic radiation overlaps two edges of the mesa.

9. The method of claim 8, wherein the two edges are opposite edges.

10. The method of claim 7, wherein the electromagnetic radiation overlaps three edges of the mesa.

11. The method of claim 7, wherein the electromagnetic radiation overlaps all edges of the mesa.

12. The method of claim 11, wherein the shape of the electromagnetic beam substantially matches the shape of the mesa.

13. The method of claim 7, wherein the electromagnetic radiation overlaps at least a portion of each of a plurality of mesas.

14. The method of claim 1, wherein removing the substrate includes chemically etching the substrate.

15. The method of claim 1, wherein removing the substrate includes lapping the substrate.

16. The method of claim 15, wherein after lapping the substrate, the substrate is chemically etched.

17. The method of claim 1, further comprising treating a top surface of the mesas prior to forming the light emitting devices.

18. The method of claim 17, wherein treating includes chemically cleaning the mesas.

19. The method of claim 17, wherein treating includes polishing the mesas.

20. The method of claim 17, further comprising depositing an insulating layer prior to polishing the mesas.

21. The method of claim 1, wherein the multilayer stack is in the form of a wafer.

22. The method of claim 21, wherein the wafer has a cross-sectional area of at least about two inches.

23. The method of claim 21, wherein the wafer has a cross-sectional area of at least about three inches

24. The method of claim 21, wherein the wafer has a cross-sectional area of at least about 12 inches.

25. The method of claim 1, wherein a particular one of the plurality of mesas is at least about 1 mm on a side.

26. The method of claim 1, wherein a particular one of the plurality of mesas is at least about 3 mm on a side.

27. The method of claim 1, wherein at least one mesa is at least about 4 mm on a side.

28. The method of claim 1, wherein at least one mesa is at least about 5 mm on a side.

29. The method of claim 1, wherein at least one mesa is at least about 6 mm on a side.

30. The method of claim 1, wherein the semiconductor layer comprises a III-V semiconductor layer.

31. The method of claim 30, wherein the III-V semiconductor layer comprises a nitride.

32. The method of claim 31, wherein the III-V semiconductor layer comprises a gallium nitride compound.

33. The method of claim 30, wherein the III-V semiconductor layer is selected from the group consisting of gallium nitride, aluminum gallium nitride, aluminum indium gallium nitride, indium gallium nitride, and combinations thereof.

34. The method of claim 1, wherein the submount comprises a material selected from the group consisting of germanium, silicon, gallium arsenide, silicon-carbide, copper, copper-tungsten, silver-tungsten, molybdenum, diamond, diamond-copper, nickel-cobalt, and combinations thereof.

35. The method of claim 1, wherein the submount is sputtered.

36. The method of claim 1, wherein the submount is electroformed.

37. The method of claim 1, wherein the substrate comprises a material selected from the group consisting of sapphire, a compound semiconductor, zinc oxide, silicon carbide, silicon, and combinations thereof.

38. The method of claim 5, wherein the electromagnetic radiation includes an absorption wavelength of the semiconductor layer.

39. The method of claim 38, wherein the electromagnetic radiation includes radiation at about 248 nanometers.

40. The method of claim 38, wherein the electromagnetic radiation includes radiation at about 355 nanometers.

41. The method of claim 1, wherein the at least one mesa has a square cross-section.

42. The method of claim 1, wherein the at least one mesa has a rectangular cross-section.

43. The method of claim 42, wherein the rectangular mesa has an aspect ratio of 16:

9.

44. The method of claim 42, wherein the rectangular mesa has an aspect ratio of 4:

3.

45. The method of claim 5, wherein the semiconductor layer is exposed to the electromagnetic radiation through the substrate.

46. The method of claim 5, further comprising heating the multi-layer stack after exposing the substrate to the electromagnetic radiation.

47. The method of claim 5, further comprising supporting the submount with an acoustically absorbing material.

48. The method of claim 47, wherein the acoustically absorbing material is a polymer.

49. The method of claim 1, further comprising, after removing the substrate, treating the semiconductor layer.

50. The method of claim 49, wherein treating the semiconductor layer removes the semiconductor layer.

51. The method of claim 49, wherein treating the semiconductor layer includes a chemical-mechanical polishing process.

52. The method of claim 49, wherein treating the semiconductor layer includes mechanical polishing.

53. The method of claim 49, wherein treating the semiconductor layer includes dry etching.

54. The method of claim 49, wherein treating the semiconductor layer includes dry etching with a substantially chemical etching component.

55. The method of claim 49, wherein treating the semiconductor layer includes a substantially physical etching component.

56. The method of claim 49, wherein treating the semiconductor layer includes wet etching.

57. The method of claim 49, wherein the semiconductor layer is a buffer layer, and treating the semiconductor layer includes removing the semiconductor layer to expose a surface of an n-doped semiconductor layer, the buffer layer being supported by the n-doped semiconductor layer before removal of the buffer layer.

58. The method of claim 1, wherein the multi-layer stack further comprises a p-doped semiconductor layer between the submount and the semiconductor layer.

59. The method of claim 58, wherein the p-doped semiconductor layer is bonded to the submount via at least one bonding layer.

60. The method of claim 58, wherein the first multi-layer stack further comprises an active region between the p-doped semiconductor layer and the semiconductor layer.

61. The method of claim 1, wherein forming at least one light emitting device from at least one of the mesas includes forming at least one light emitting device from at least 10% of the mesas.

62. The method of claim 2, wherein forming at least one light emitting device from at least one of the mesas includes forming at least one light emitting device from at least 25% of the mesas.

63. The method of claim 2, wherein forming at least one light emitting device from at least one of the mesas includes forming at least one light emitting device from at least 50% of the mesas.

64. The method of claim 2, wherein forming at least one light emitting device from at least one of the mesas includes forming at least one light emitting device from at least 75% of the mesas.

65. The method of claim 2, wherein forming at least one light emitting device from at least one of the mesas includes forming at least one light emitting device from at least 80% of the mesas.

66. The method of claim 2, wherein forming at least one light emitting device from at least one of the mesas includes forming at least one light emitting device from at least 90% of the mesas.

67. The method of claim 1, wherein the semiconductor layer is supported by the substrate in the multilayer stack.

68. The method of claim 67, wherein the quantum well containing region is supported by the semiconductor layer.

69. The method of claim 1, wherein the at least one mesa is at least about 1 micron in height.

70. The method of claim 1, wherein the at least one mesa is at least about ½

micron in height.

71. The method of claim 1, wherein the at least one mesa is at least about 2 microns in height.

72. The method of claim 1, wherein the at least one mesa is at least about 3 microns in height

73. The method of claim 1, wherein the at least one mesa is at least about 4 microns in height

74. The method of claim 1, wherein the at least one mesa is at least about 5 microns in height

75. The method of claim 1, wherein the at least one mesa is at least about 6 microns in height.

76. The method of claim 1, wherein etching the quantum well containing region includes reactive ion etching.

77. The method of claim 76, wherein the reactive ion etching is chlorine based.

78. The method of claim 1, wherein etching the quantum well containing region includes etching a portion of the semiconductor layer.

79. The method of claim 1, wherein etching the quantum well containing region includes etching through the semiconductor layer to expose the substrate.

80. The method of claim 1, further comprising:

patterning a surface of at least one of the mesas; and

forming a light emitting device from the at least one of the mesas.

81. The method of claim 80, wherein patterning a surface of at least one of the mesas includes:

depositing a resist material on at least some of the plurality of mesas; and

imprinting the resist material using a mold.

82. The method of claim 81, wherein the mold is a flexible mold.

83. The method of claim 82, wherein the flexible mold comprises Ni.

84. The method of claim 82, wherein the flexible mold comprises a polymer.

85. The method of claim 84, wherein the polymer includes polyvinyl alcohol.

86. The method of claim 80, wherein patterning a surface of at least one of the mesas includes:

forming an array of self-assembled nano-particles on the surface of at least some of the mesas.

87. The method of claim 86, wherein the self-assembled nano-particles include polystyrene beads.

88. The method of claim 87, further comprising:

depositing a material onto the mesas and the nano-particles; and

removing the nano-particles and portions of the material supported by the nano-particles.

89. The method of claim 86 where the nano-particles are of at least two different sizes.

90. The method of claim 87 wherein the polystyrene beads include polystyrene beads of at least two different sizes.

91. The method of claim 88 further comprising transferring the pattern into a portion of the semiconductor layer.

92. The method of claim 91 further comprising depositing ohmic contacts onto the surface of the mesa.

93. The method of claim 86 wherein forming an array of self-assembled nano-particles includes forming the array of self-assembled nano-particles using drying conditions different than equilibrium conditions.

94. The method of claim 86 wherein the array of self-assembled nano-particles forms a complex periodic pattern.

95. The method of claim 86 wherein the array of self-assembled nano-particles forms a detuned periodic pattern.

96. The method of claim 86 wherein the array of self-assembled nano-particles forms a quasi-crystalline pattern.

97. The method of claim 86 wherein the array of self-assembled nano-particles forms a non-periodic pattern.

98. The method of claim 86 wherein the array of self-assembled nano-particles forms a periodic pattern.

99. A method of making a light emitting device, the method comprising:

providing an etched multilayer stack including a plurality of mesas supported by a substrate, at least some of the mesas including a semiconductor layer and a quantum well containing region;

bonding the etched multilayer stack to a submount;

removing the substrate; and

forming at least one light emitting device from at least one of the mesas.

100. A method comprising:

providing a first article including a substrate that supports a plurality of mesas; and

forming a second article from the first article, wherein the second article includes a submount supporting at least some of the plurality of mesas.

101. The method of claim 100, wherein the second article does not include the substrate.

102. The method of claim 100, wherein the mesas include a quantum well containing region.

103. The method of claim 100, wherein a particular one of the plurality of mesas is at least about 1 mm on a side.

104. The method of claim 100, wherein a particular one of the plurality of mesas is at least about 3 mm on a side.

105. The method of claim 100, wherein at least one mesa is at least about 4 mm on a side.

106. The method of claim 100, wherein at least one mesa is at least about 5 mm on a side.

107. The method of claim 100, wherein at least one mesa is at least about 6 mm on a side.

108. The method of claim 100, wherein the mesas include a semiconductor layer.

109. The method of claim 108, wherein the semiconductor layer comprises a III-V semiconductor layer.

110. The method of claim 108, wherein the III-V semiconductor layer comprises a nitride.

111. The method of claim 108, wherein the III-V semiconductor layer comprises a gallium nitride compound.

112. A method comprising:

providing a multilayer stack including a substrate and a semiconductor layer;

etching at least a portion of the multilayer stack to provide an etched multilayer stack including a plurality of gas accumulation regions;

bonding the etched multilayer stack to a submount;

exposing the semiconductor layer to electromagnetic radiation to partially decompose the semiconductor layer, wherein exposing the semiconductor layer to electromagnetic radiation generates gas and the gas accumulates in the gas accumulation regions.

113. The method of claim 112, wherein the gas accumulation regions form a connected network.

114. The method of claim 113, wherein the connected network extends to the edge of the multilayer stack.

115. A method comprising:

providing a multilayer stack including a substrate, a semiconductor layer, and a bonding layer;

etching at least a portion of the bonding layer to provide an etched multilayer stack; and

bonding the etched multilayer stack to a submount.

116. The method of claim 115, further comprising removing the substrate.

117. The method of claim 115, wherein etching at least a portion of the bonding layer includes etching a grid pattern in the bonding layer.

118. The method of claim 115, wherein etching at least a portion of the bonding layer includes etching a plurality of parallel lines in the bonding layer.

119. The method of claim 115, wherein the gas accumulation regions include etched regions separating a plurality of mesas.

120. A method for bonding a multilayer stack to a submount, the method comprising:

providing a multilayer stack including a substrate, a semiconductor layer, and a bonding layer;

determining an amount of non-planarity present in the multilayer stack;

determining an amount of etching necessary to reduce the non-planarity to a predetermined level; and

etching the multilayer stack based on the determined amount of etching.

121. The method of claim 120, further comprising bonding the multilayer stack to a submount.

122. The method of claim 120, wherein determining an amount of etching necessary to reduce the non-planarity includes determining a depth of an etch necessary to reduce the non-planarity.

123. The method of claim 120, wherein determining an amount of etching necessary to reduce the bow includes determining a number of etch locations necessary to reduce the non-planarity.

124. The method of claim 120, wherein the non-planarity includes wafer bow.

125. The method of claim 120, wherein the non-planarity includes warp.