CMOS image sensor and method for manufacturing the same

• US 20050064620A1
• Filed: 12/23/2003
• Published: 03/24/2005
• Est. Priority Date: 09/22/2003
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Inventors: Han, Chang Hun
• Granted Patent: US 7,217,967 B2
• Time in Patent Office: Days
• US Class Current: 438/57
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/1463 Pixel isolation structures

Abstract

A CMOS image sensor and a manufacturing method thereof are disclosed. The gates of the transistors are formed in an active region of a unit pixel, and at the same time, a passivation layer is formed on an edge portion of the active region of a photodiode to have the same laminate structure as the gates of the transistors. Impurities for a diffusion region of the photodiode are ion-implanted into the active region for the photodiode, after the laminate structure is formed. The passivation layer prevents the edge portion from being damaged by ion implantation at the boundary or interface between the photodiode diffusion region and an isolation layer, which reduces dark current and/or leakage current of the CMOS image sensor.

Claims

1. A method for manufacturing a CMOS image sensor, the method comprising the steps of:

a) forming an isolation layer on a semiconductor substrate so as to define an active region for a unit pixel;

b) forming (i) a passivation layer over a boundary between said isolation layer and the active region and (ii) at least one transistor gate structure on said semiconductor substrate; and

c) implanting impurities into a portion of the active region to form a diffusion region for a photodiode.

2. The method for manufacturing a CMOS image sensor as claimed in claim 1, wherein said passivation layer comprises a first layer of a gate insulating material and a second layer of a gate electrode material.

3. The method for manufacturing a CMOS image sensor as claimed in claim 2, wherein said first layer comprises a thermal oxide layer and said second layer comprises a highly doped polysilicon layer.

4. The method for manufacturing a CMOS image sensor as claimed in claim 3, wherein said second layer further comprises a silicide layer on said polysilicon layer.

5. The method for manufacturing a CMOS image sensor as claimed in claim 1, wherein said semiconductor substrate comprises a P⁺⁺ type silicon substrate having a P⁻

type epitaxial layer thereon, and said diffusion region comprises an n⁻

type diffusion region.

6. The method for manufacturing a CMOS image sensor as claimed in claim 5, further comprising the step of performing a P⁰ type ion implantation into said n⁻

type diffusion region.

7. The method for manufacturing a CMOS image sensor as claimed in claim 1, wherein said passivation layer and said at least one transistor gate structure are formed simultaneously.

8. The method for manufacturing a CMOS image sensor as claimed in claim 1, further comprising the step of implanting a dopant into said active region adjacent to said transistor gate structure to from source/drain diffusion regions for a transistor.

9. A CMOS image sensor comprising:

a) a semiconductor substrate having an isolation region and an active region for a unit pixel;

b) at least one transistor formed on said semiconductor substrate in said unit pixel; and

c) a diffusion region for a photodiode, wherein said diffusion region is located a distance away from said isolation region.

10. The CMOS image sensor as claimed in claim 9, further comprising a passivation layer over a boundary between said isolation region and the active region on said semiconductor substrate.

11. The CMOS image sensor as claimed in claim 10, wherein said passivation layer comprises a first layer of a gate insulating material and a second layer of a gate electrode material.

12. The CMOS image sensor as claimed in claim 11, wherein said transistor comprises said first layer of said gate insulating material and said second layer of said gate electrode material.

13. The CMOS image sensor as claimed in claim 12, wherein said first layer comprises a thermal oxide layer and said second layer comprises a highly doped polysilicon layer.

14. The CMOS image sensor as claimed in claim 13, wherein said second layer further comprises a silicide layer on said polysilicon layer.

15. The CMOS image sensor as claimed in claim 9, wherein said isolation region comprises an isolation layer.

16. The CMOS image sensor as claimed in claim 15, wherein an outer boundary of said isolation layer defines a boundary or interface between said isolation region and the active region.

17. The CMOS image sensor as claimed in claim 15, wherein said isolation layer comprises a shallow trench isolation layer.

18. The CMOS image sensor as claimed in claim 9, wherein said semiconductor substrate comprises a P⁺⁺ type silicon substrate having a P⁻

type epitaxial layer thereon, and said diffusion region comprises an n⁻

type diffusion region.

19. The CMOS image sensor as claimed in claim 18, further comprising a P⁰ type diffusion region on said n⁻

type diffusion region.

20. The CMOS image sensor as claimed in claim 12, wherein said transistor further comprises source/drain diffusion regions adjacent to said first and second layers of said transistor.