Stackable motherboard and related sensor systems

• US 20050073819A1
• Filed: 11/26/2004
• Published: 04/07/2005
• Est. Priority Date: 05/17/2002
• Status: Active Grant

• Current Assignee: Pixel Velocity Incorporated
• Original Assignee: Pixel Velocity Incorporated
• Inventors: McCubbrey, David L.
• Granted Patent: US 7,451,410 B2
• Time in Patent Office: Days
• US Class Current: 361/785
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H05K 1/144 Stacked arrangements of planar printed circuit boards

Abstract

The stackable motherboard 10 of the first embodiment includes: a circuit board 12 having a first side 14 and a second side 16 opposite the first side 14, a processor 16 mounted on the circuit board 12, a first peripheral interconnect 18, and a second peripheral interconnect 20. The stackable motherboard 10 also preferably includes: a first motherboard interconnect 22 mounted on the first side 14 of the circuit board 12 and adapted to communicate data between the processor 16 and a first auxiliary motherboard, and a second motherboard interconnect 24 mounted on the second side 16 of the circuit board 12 and adapted to communicate data between the processor 16 and a second auxiliary motherboard.

Claims

1. A stackable motherboard, comprising:

a circuit board having a first side and a second side opposite the first side;

a processor mounted on the circuit board;

a first peripheral interconnect coupled to the processor;

a second peripheral interconnect coupled to the processor;

a first motherboard interconnect coupled to the processor, mounted on the first side of the circuit board, and adapted to communicate data between the processor and a first auxiliary motherboard; and

a second motherboard interconnect coupled to the processor, mounted on the second side of the circuit board, and adapted to communicate data between the processor and a second auxiliary motherboard.

2. The stackable motherboard of claim 1, wherein the processor includes a reconfigurable processor.

3. The stackable motherboard of claim 2, wherein the reconfigurable processor includes a field programmable gate array.

4. The stackable motherboard of claim 1, wherein the first motherboard interconnect includes an output portion adapted to communicate data from the processor to a first auxiliary motherboard, and wherein the first motherboard interconnect includes an input portion adapted to communicate data from the first auxiliary motherboard to the processor.

5. The stackable motherboard of claim 4, wherein the second motherboard interconnect includes an input portion adapted to communicate data from the second auxiliary motherboard to the processor, wherein the second motherboard interconnect includes an output portion adapted to communicate data from the processor to the second auxiliary motherboard.

6. The stackable motherboard of claim 1, wherein the first motherboard interconnect and the second motherboard interconnect are complimentarily located on either side of the motherboard.

7. The stackable motherboard of claim 1, further including a first memory coupled to the processor.

8. The stackable motherboard of claim 7, further including a second memory coupled to the processor.

9. The stackable motherboard of claim 1, further including a bus coupled to the processor and adapted to supply at least one of the following:

power, global signals, and programming.

10. A sensor system, comprising:

a sensor device adapted to receive information;

a first stackable motherboard as defined in claim 1;

and

a daughterboard adapted to communicate the received information between the sensor device and the first peripheral interconnect of the first stackable motherboard.

11. The sensor system of claim 10, wherein the sensor device is further adapted to capture visible images.

12. The sensor system of claim 11, further including a second stackable motherboard as defined in claim 1, wherein the first motherboard interconnect of the first stackable motherboard is adapted to communicate data with the second motherboard interconnect of the second stackable motherboard.

13. The sensor system of claim 10, wherein the sensor device is further adapted to capture ultrasound echoes.

14. The sensor system of claim 13, further including a second stackable motherboard as defined in claim 1, wherein the first motherboard interconnect of the first stackable motherboard is adapted to communicate data with the second motherboard interconnect of the second stackable motherboard.

15. The sensor system of claim 14, further including a third stackable motherboard as defined in claim 1, wherein the first motherboard interconnect of the second stackable motherboard is adapted to communicate data with the second motherboard interconnect of the third stackable motherboard.

16. A method of supplying motherboards and forming at least one sensor system comprising the following steps:

a) providing a series of stackable motherboards, each as defined in claim 1;

b) providing a series of first sensor devices, each adapted to capture visible images;

c) providing a series of first daughterboards, each adapted to communicate the captured visible images between a first sensor device and a first peripheral interconnect of a stackable motherboard; and

d) combining one of the first daughterboards, one of the first sensor devices, and one or more of the stackable motherboards to form a first sensor system adapted to capture and process visible images.

17. The method of claim 16, wherein step (d) includes combining one of the first daughterboards, one of the first sensor devices, and two or more of the stackable motherboards to form a first sensor system adapted to capture and process visible images.

18. The method of claim 17, further including the following steps:

e) providing a series of second sensor devices, each adapted to capture ultrasound echoes;

f) providing a series of second daughterboards, each adapted to communicate the captured ultrasound echoes between a second sensor device and a first peripheral interconnect of a stackable motherboard; and

g) combining one of the second daughterboards, one of the second sensor devices, and one or more of the stackable motherboards to form a second sensor system adapted to capture and process ultrasound echoes.

19. The method of claim 18, wherein step (g) includes combining one of the second daughterboards, one of the second sensor devices, and two or more of the stackable motherboards to form a second sensor system adapted to capture and process ultrasound echoes.

20. The method of claim 19, wherein step (g) includes combining one of the second daughterboards, one of the second sensor devices, and three or more of the stackable motherboards to form a second sensor system adapted to capture and process ultrasound echoes.