Method and system for defining and controlling algorithmic elements in a graphics display system

• US 20050086669A1
• Filed: 10/22/2004
• Published: 04/21/2005
• Est. Priority Date: 03/07/2000
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Toelle, Michael A., Boyd, Charles N.
• Granted Patent: US 7,800,606 B2
• Time in Patent Office: Days
• US Class Current: 719/328
• CPC Class Codes: G06T 15/005 General purpose rendering architectures

Abstract

An API is provided that enables programmability of a 3D chip, wherein programming or algorithmic elements written by the developer can be downloaded to the chip, thereby programming the chip to perform those algorithms. A developer writes a routine that is downloadable to a 3D graphics chip. There are also a set of algorithmic elements that are provided in connection with the API that have already been programmed for the developer, that are downloadable to the programmable chip for improved performance. Thus, a developer may download preexisting API objects to a 3D graphics chip. A developer adheres to a specific format for packing up an algorithmic element, or set of instructions, for implementation by a 3D graphics chip. The developer packs the instruction set into an array of numbers, by referring to a list of ‘tokens’ understood by the 3D graphics chip. This array of numbers in turn is mapped correctly to the 3D graphics chip for implementation of the algorithmic element by the 3D graphics chip.

Claims

1. A method for processing data in a graphics system by a graphics processing unit (GPU) on behalf of a host, comprising:

receiving by the GPU at least one host application programming interface (API) call and unpacking a plurality of algorithmic elements from the host API call; and

mapping the unpacked plurality of algorithmic elements to at least one computational subunit of the GPU, thereby readying the at least one computational subunit to perform the functionality defined by the plurality of algorithmic elements.

2. A method according to claim 1, further comprising:

processing graphics data specified by at least one host API call according to the functionality represented by the plurality of algorithmic elements.

3. A method according to claim 2, wherein said at least one computational subunit of the GPU includes a vertex shader subunit and said graphics data is vertex data specifying at least one vertex of a graphics object.

4. A method according to claim 2, wherein said at least one computational subunit of the GPU includes a pixel shader subunit and said graphics data is pixel data specifying at least one pixel of a graphics object.

5. A method according to claim 1, wherein said receiving by the GPU at least one host API call includes receiving an array of numbers included in the host API call.

6. A method according to claim 5, wherein said unpacking includes unpacking the plurality of algorithmic elements from the array of numbers.

7. A method according to claim 6, whereby said unpacking includes unpacking the plurality of algorithmic elements from the array of numbers, by referring to a list of tokens interpretable by the GPU.

8. A method according to claim 1, whereby said mapping includes mapping the unpacked plurality of algorithmic elements to at least one procedural shader of the GPU according to a pre-defined protocol.

9. A method according to claim 1, wherein the plurality of algorithmic elements comprise instructions for at least one of lighting, colorizing, mapping, texturizing, surfacing, shading, and enhancing an image.

10. A method according to claim 1, wherein said unpacking includes unpacking the plurality of algorithmic elements based on a declaration portion included in said host API call.

11. A method according to claim 10, wherein said declaration portion includes assignment information for assigning at least one input register of the at least one computational subunit to corresponding data streams specified by said host API call.

12. A method according to claim 11, wherein said assignment information is for assigning at least one input register to a data element within a data stream.

13. A method according to claim 12, wherein said assignment information is for assigning at least one input register to a vertex element within a vertex stream.

14. A method according to claim 13, wherein the vertex element of the vertex stream is identified by a byte offset within the vertex stream and a type.

15. A method according to claim 10, wherein said declaration portion includes assignment information for assigning at least one input register of the at least one computational subunit to data output from a tessellator subunit of the GPU.

16. A method according to claim 10, wherein said declaration portion includes assignment information for assigning at least one value to at least one memory location reserved for constants in the at least one computational subunit.

17. A method according to claim 16, wherein said assignment information includes a token that specifies a plurality of values for at least one contiguous group of memory locations reserved for constants in the at least one computational subunit.

18. A method according to claim 16, wherein said declaration portion includes assignment information for updating an arbitrary subset of the memory locations reserved for constants, including assignment information for overwriting the device state.

19. A method according to claim 10, wherein said declaration portion includes at least one stream selector token followed by a contiguous set of stream data definition tokens.

20. A method according to claim 19, wherein the contiguous set of stream data definition tokens define a stream, including the set of elements within the stream, the order in which the elements of the stream appear, the type of each element, and the register into which to load each element.

21. A method according to claim 20, wherein a stream is allowed to include at least one element which is not loaded into a register.

22. A video card having means for performing the method of claim 1.

23. A graphics processing unit having means for performing the method of claim 1.

24. A computer readable medium comprising computer executable instructions for performing the method of claim 1.

25. A method for processing data in a graphics system by a procedural shader computational subunit included on a graphics processing unit (GPU), comprising:

receiving a plurality of algorithmic elements for performing procedural shading algorithms on graphics data, wherein the plurality of algorithmic elements are received by the GPU from at least one host application programming interface (API) call; and

distributing the plurality of algorithmic elements to corresponding storage locations of the procedural shader based on a pre-defined protocol, enabling the procedural shader to perform the procedural shading algorithms represented by the plurality of algorithmic elements.

26. A method according to claim 25, wherein the procedural shader computational subunit is a vertex shader.

27. A method according to claim 25, wherein the procedural shader computational subunit is a pixel shader.

28. A method according to claim 25, further comprising:

processing graphics data according to the functionality represented by the plurality of algorithmic elements.

29. A method according to claim 25, wherein said receiving includes receiving an array of numbers.

30. A method according to claim 29, whereby the plurality of algorithmic elements include an array of numbers.

31. A method according to claim 30, whereby the plurality of algorithmic elements are distributed according to said distributing based on the array of numbers via reference to a list of tokens interpretable by the GPU.

32. A method according to claim 25, wherein the plurality of algorithmic elements comprise instructions for customizing the procedural shader computational subunit to perform at least one of lighting, colorizing, mapping, texturizing, surfacing, shading and enhancing an image.

33. A method according to claim 25, wherein said receiving includes receiving a declaration portion from the at least one host API call for use in said distributing of the plurality of algorithmic elements to the appropriate storage locations.

34. A method according to claim 33, wherein said declaration portion includes assignment information for assigning at least one input register of the procedural shader computational subunit to a corresponding graphics data stream specified by said host API call.

35. A method according to claim 34, wherein said assignment information is for binding a specific input register to a single element within the graphics data stream.

36. A method according to claim 33, wherein said declaration portion includes assignment information for assigning at least one input register of the procedural shader computational subunit to data output from a tessellator subunit of the GPU.

37. A method according to claim 33, wherein said declaration portion includes assignment information for assigning values to constant memory of the procedural shader computational subunit.

38. A method according to claim 37, wherein said assignment information includes a token that specifies values for one or more contiguous groups of constant registers of the constant memory of the procedural shader computational subunit.

39. A method according to claim 37, wherein said declaration portion includes assignment information for updating an arbitrary subset of the constant memory.

40. A method according to claim 33, wherein said declaration portion includes at least one stream selector token followed by a contiguous set of stream data definition tokens.

41. A method according to claim 40, wherein the contiguous set of stream data definition tokens define a stream, including the set of elements within the stream, the order in which the elements of the stream appear, the type of each element, and the register into which to load each element.

42. A video card having means for performing the method of claim 25.

43. A graphics processing unit having means for performing the method of claim 25.

44. A computer readable medium comprising computer executable instructions for performing the method of claim 25.