CMOS image sensor and method for fabricating the same

• US 20050088556A1
• Filed: 10/28/2004
• Published: 04/28/2005
• Est. Priority Date: 10/28/2003
• Status: Active Grant

• Current Assignee: III Holdings 4, LLC
• Original Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Inventors: Han, Chang Hun
• Granted Patent: US 7,232,712 B2
• Time in Patent Office: Days
• US Class Current: 348/308
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

A CMOS image sensor and a method for fabricating the same is disclosed, to decrease a darkcurrent generated in the boundary between a diffusion area of a photodiode and a device isolation layer, which includes a first conductive type semiconductor substrate having an active area and a device isolation area, the active area including a photodiode and a transistor; a device isolation layer formed in the device isolation area of the semiconductor substrate; a second conductive type diffusion area formed in the photodiode of the semiconductor substrate at a predetermined interval from the device isolation layer; a gate insulating layer and a gate electrode formed in the transistor of the semiconductor substrate; and a first conductive type first diffusion area formed in the semiconductor substrate of the boundary between the second conductive type diffusion area and the device isolation layer.

Claims

1. A CMOS image sensor comprising:

a first conductive type semiconductor substrate having an active area and a device isolation area, the active area including a photodiode and a transistor;

a device isolation layer formed in the device isolation area of the semiconductor substrate;

a second conductive type diffusion area formed in the photodiode of the semiconductor substrate at a predetermined interval from the device isolation layer;

a gate insulating layer and a gate electrode formed in the transistor of the semiconductor substrate; and

a first conductive type first diffusion area formed in the semiconductor substrate of the boundary between the second conductive type diffusion area and the device isolation layer.

2. The CMOS image sensor of claim 1, further comprising a passivation layer on the semiconductor substrate of the boundary between the device isolation layer and the photodiode.

3. The CMOS image sensor of claim 2, wherein the passivation layer is formed of an oxide or a nitride.

4. The CMOS image sensor of claim 2, wherein a sidewall insulating layer is formed at the side of the gate electrode, and the passivation layer is formed of the same material as the sidewall insulating layer.

5. The CMOS image sensor of claim 2, wherein the passivation layer is formed in a deposition structure of the gate insulating layer and the gate electrode of the transistor.

6. The CMOS image sensor of claim 2, wherein the first conductive type first diffusion area is formed below the passivation layer.

7. The CMOS image sensor of claim 1, wherein the first conductive type first diffusion area is formed deeper than the second conductive type diffusion area.

8. The CMOS image sensor of claim 1, wherein the first conductive type semiconductor substrate has a first conductive type epitaxial layer.

9. The CMOS image sensor of claim 1, further comprising a first conductive type second diffusion area in the surface of the second conductive type diffusion area of the photodiode.

10. The CMOS image sensor of claim 9, wherein the first conductive type first diffusion area has impurity ions of a higher concentration than that of impurity ions of the first conductive type second diffusion area.

11. The CMOS image sensor of claim 1, wherein the device isolation layer has a higher surface than that of the semiconductor substrate.

12. The CMOS image sensor of claim 11, further comprising an ion implantation prevention layer at the side of the device isolation layer having the higher surface than that of the semiconductor substrate.

13. The CMOS image sensor of claim 12, wherein the first conductive type first diffusion area is formed below the ion implantation prevention layer.

14. A method for fabricating a CMOS image sensor comprising:

forming a device isolation layer in a device isolation area of a first conductive type semiconductor substrate, so as to define an active area having a photodiode and a transistor;

forming a gate insulating layer, a gate electrode, and a sidewall insulating layer in the transistor, and forming a passivation layer on the semiconductor substrate of the boundary between the device isolation layer and the photodiode;

forming a second conductive type diffusion area in the photodiode of the active area; and

forming a first conductive type first diffusion area in the semiconductor substrate of the boundary between the second conductive type diffusion area and the device isolation layer.

15. The method of claim 14, wherein the first conductive type first diffusion area is formed by tilt-implanting first conductive type impurity ions with the passivation layer.

16. The method of claim 14, wherein the first conductive type first diffusion area is formed deeper than the second conductive type diffusion area.

17. The method of claim 14, further comprising the step of forming a first conductive type second diffusion area in the surface of the second conductive type diffusion area of the photodiode.

18. The method of claim 17, wherein the first conductive type first diffusion area has impurity ions of a higher concentration than that of impurity ions of the first conductive type second diffusion area.

19. The method of claim 17, wherein the first conductive type second diffusion area is formed at a predetermined interval from the gate electrode.

20. The method of claim 14, wherein the passivation layer is formed of the same material as the sidewall insulating layer.

21. The method of claim 14, wherein the passivation layer is formed in a deposition structure of the gate insulating layer and the gate electrode of the transistor.

22. A method for fabricating a CMOS image sensor comprising:

forming a projected device isolation layer having a higher surface than that of a first conductive type semiconductor substrate, in a device isolation area, so as to define an active area having a photodiode and a transistor;

forming an ion implantation prevention layer at the sidewall of the projected device isolation layer;

forming a gate insulating layer and a gate electrode in the transistor;

forming a second conductive type diffusion area in the photodiode of the active area; and

forming a first conductive type first diffusion area in the semiconductor substrate of the boundary between the second conductive type diffusion area and the device isolation layer.

23. The method of claim 22, wherein the process of forming the device isolation layer includes the steps of:

forming an oxidizing insulating layer on the semiconductor substrate;

selectively removing the oxidizing insulating layer so as to expose the semiconductor substrate of the device isolation area;

forming a trench by etching the exposed semiconductor substrate;

depositing an insulating layer to fill the trench, and planarizing the insulating layer to expose the surface of the oxidizing insulating layer; and

removing the oxidizing insulating layer.

24. The method of claim 23, further comprising the step of forming a thermal oxide layer on an inner surface of the trench after forming the trench.

25. The method of claim 22, wherein the first conductive type first diffusion area is formed by tilt-implanting first conductive type impurity ions.

26. The method of claim 22, wherein the first conductive type first diffusion area is formed deeper than the second conductive type diffusion area.

27. The method of claim 22, further comprising the step of forming a first conductive type second diffusion area in the surface of the second conductive type diffusion area of the photodiode.

28. The method of claim 27, wherein the first conductive type first diffusion area has impurity ions of a higher concentration than that of impurity ions of the first conductive type second diffusion area.

29. The method of claim 22, wherein the ion implantation prevention layer is formed of a nitride layer.