System for optimizing anti-fuse repair time using fuse id

• US 20050091560A1
• Filed: 07/21/2003
• Published: 04/28/2005
• Est. Priority Date: 08/07/1996
• Status: Active Grant

• Current Assignee: Ray Beffa
• Original Assignee: Ray Beffa
• Inventors: Beffa, Ray
• Granted Patent: US 7,069,484 B2
• Time in Patent Office: Days
• US Class Current: 714/718
• CPC Class Codes: G01R 31/318371 Methodologies therefor, e.g. algorithms, procedures
• CPC Class Codes: G01R 31/319 Tester hardware, i.e. output processing circuits
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G11C 29/08 Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
• CPC Class Codes: G11C 29/10 Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
• CPC Class Codes: G11C 29/26 Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair

Abstract

A method and apparatus for testing semiconductor memory chips, such as DRAMs, having a plurality of memory cells or bits. Each memory chip has a unique identifier stored in a database. Tests are performed on the memory chips and when a memory chip fails a test, the memory chip is placed in a repair bin and a test identifier is stored in the database in association with the memory chip identifier. In order to repair the memory chip, failed tests are read out of the database and such tests are again performed on the failed memory chip in order to determine which memory cell in the memory chip is faulty. The failed memory cells are then repaired.

Claims

1-32. -32. (canceled)

33. A method for testing a plurality of integrated circuits, including the steps of:

performing a plurality of tests on the plurality of integrated circuits, each of said integrated circuits having a unique identifier stored in a machine readable device;

identifying integrated circuits that failed at least one of the plurality of tests by reading said unique identifier and identifying tests failed by the integrated circuits; and

for each of said plurality of integrated circuits which has failed at least one of the plurality of tests,

creating a set of at least one test as a function of the unique identifier of a failed chip and repeating said set of at least one test the failed chip.

34. The method of claim 33, wherein said machine readable device is a set of anti-fuses and said unique identifier is read by reading said set of anti-fuses.

35. The method of claim 33, wherein said machine readable device is a non-volatile memory circuit and said unique identifier is read by reading said non-volatile memory circuit.

36. The method of claim 35, wherein said non-volatile memory circuit is FLASH memory circuit and said unique identifier is read by reading said FLASH memory circuit.

37. The method of claim 35, wherein said non-volatile memory circuit is electrical programmable read only memory (EPROM) circuit and said unique identifier is read by reading said EPROM memory circuit.

38. The method of claim 35, wherein said non-volatile memory circuit is read only memory (ROM) circuit and said unique identifier is read by reading said ROM memory circuit.

39. The method of claim 33, wherein said machine readable device is a content addressable memory circuit (CAM) and said unique identifier is read by reading said CAM memory circuit.

40. An apparatus for testing a plurality of integrated circuits, comprising:

means for performing a plurality of tests on the plurality of integrated circuits;

means for reading a unique identifier from each integrated circuits that failed at least one of the plurality of tests and identifying tests failed by the integrated circuits; and

means for repeating at least one identified failed test on each of the integrated circuits which failed at least one test.

41. The apparatus of claim 40, wherein said means for reading comprises a circuit for reading the unique identifier from a set of anti-fuses.

42. The apparatus of claim 40, wherein said means for reading comprises a circuit for reading the unique identifier from a non-volatile memory.

43. The apparatus of claim 42, wherein said means for reading comprises a circuit for reading the unique identifier from a FLASH memory.

44. The apparatus of claim 42, wherein said means for reading comprises a circuit for reading the unique identifier from a electrical programmable read only memory (EPROM).

45. The apparatus of claim 42, wherein said means for reading comprises a circuit for reading the unique identifier from a read only memory (ROM).

46. The apparatus of claim 40, wherein said means for reading comprises a circuit for reading the unique identifier from a content addressable memory (CAM).

47. An apparatus for testing a plurality of integrated circuits, said apparatus comprising:

a testing device for performing a plurality of tests on said plurality of integrated circuits, each of said plurality of integrated circuits having a unique circuit identifier stored in an identification circuit; and

a processor to control said testing device, said processor identifying each of said plurality of integrated circuits that failed at least one of said plurality of tests and identifying tests failed by each of said plurality of integrated circuits,

wherein said testing device repeats at least one identified failed test on each integrated circuits that failed at least one of said plurality of tests.

48. The apparatus of claim 47, wherein said identification circuit is a set of anti-fuses.

49. The apparatus of claim 47, wherein said identification circuit is a non-volatile memory.

50. The apparatus of claim 49, wherein said non-volatile memory is a FLASH memory.

51. The apparatus of claim 49, wherein said non-volatile memory is a electrical programmable read only memory (EPROM).

52. The apparatus of claim 49, wherein said non-volatile memory is a read only memory (ROM).

53. The apparatus of claim 47, wherein said identification circuit is a content addressable memory (CAM).

54. A system comprising:

a device tester adapted to perform a principal functional test on an integrated circuit having one or more functional circuit portions and produce principal result information indicating respective operation or failure of said one or more functional circuit portions;

a reader adapted to read an identification device on said integrated circuit so as to ascertain an identity of said integrated circuit; and

a recording medium adapted to record said identity and said result information and maintain an association therebetween.

55. The system of claim 54, wherein said identification device is a set of anti-fuses.

56. The system of claim 54, wherein said identification device is a non-volatile memory.

57. The system of claim 56, wherein said non-volatile memory is a FLASH memory.

58. The system of claim 56, wherein said non-volatile memory is a electrical programmable read only memory (EPROM).

59. The system of claim 56, wherein said non-volatile memory is a read only memory (ROM).

60. The system of claim 54, wherein said identification device is a content addressable memory (CAM).