Array substrate for a liquid crystal display device and method for fabricating thereof

• US 20050094045A1
• Filed: 12/06/2004
• Published: 05/05/2005
• Est. Priority Date: 09/04/2000
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Chae, Gee-Sung
• Granted Patent: US 7,072,004 B2
• Time in Patent Office: Days
• US Class Current: 349/40
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/136204 Arrangements to prevent high voltage or static electricity failures
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line

Abstract

An LCD fabricated by forming gate lines, gate electrodes, gate pads, vertical patterns, and a first gate shorting bar on a substrate, forming channels over the gate electrodes, forming data lines, source electrodes, drain electrodes, and a second shorting bar, forming a passivation layer, patterning the passivation layer to form drain contact holes to the drain electrodes, data pad contact holes to the data pads, first connecting contact holes to the first gate shorting bar, second connecting contact holes to the second gate shorting bar, and etching holes to the vertical patterns, forming a transparent conductive layer, and patterning the transparent conductive layer to form pixel electrodes, first pad connectors that connect odd numbered gate pads to the first gate shorting bar, and second pad connectors that connect the even numbered gate pads to the second gate shorting bar, wherein the vertical patterns are etched via the etching holes.

Claims

1-6. -6. (canceled)

7. A method of fabricating an array substrate, comprising:

forming a first metal layer on a substrate;

patterning the first metal layer to form a first gate shorting bar, a vertical pattern, a plurality of odd gate lines, each having an associated odd gate pad and gate electrodes, and a plurality of even gate lines, each having an associated even gate pad and gate electrodes, wherein the vertical pattern electrically connects the odd gate pads and the even gate pads together;

forming a gate insulation layer over the substrate and over the patterned first metal layer;

forming an active layer and an ohmic contact layer over each gate electrode;

forming a second metal layer over the gate insulation layer and over the ohmic contact layers;

patterning the second metal layer to form a second shorting bar and a plurality of data lines, a plurality of source electrodes, and a plurality of drain electrodes, wherein each source electrode and each drain electrode is formed over an associated ohmic contact layer;

forming a passivation layer over the patterned second metal layer;

patterning the passivation layer to form drain contact holes to the drain electrodes, odd gate pad contact holes to the odd gate pads, even gate pad contact holes to the even gate pads, first connecting contact holes to the first gate shorting bar, second connecting contact holes to the second gate shorting bar, and etching holes to the vertical pattern;

forming a transparent conductive layer over the patterned passivation layer; and

patterning the transparent conductive layer to form pixel electrodes, first pad connectors that electrically connect the first gate shorting bar to associated odd gate pads via the first connecting contact holes and via the odd gate pad contact holes, and second pad connectors that electrically connect the second gate shorting bar to associated even gate pads via the second connecting contact holes and via the even gate pad contact holes;

wherein patterning the transparent conductive layer etches the vertical pattern via the etching holes such that the odd gate pads are electrically isolated from the even gate pads.

8. The method of fabricating an array substrate according to claim 7, wherein the odd gate pads are arranged along an end of the odd gate lines, wherein the even gate pads are arranged along an end of the even gate lines, and wherein the first gate shorting bar is spaced apart from and parallel to the vertical pattern.

9. The method of fabricating an array substrate according to claim 7, wherein each source electrode extends from an associated data line, and wherein each drain electrode is spaced apart from an associated source electrode.

10. The method of fabricating an array substrate according to claim 7, wherein forming a first metal layer on a substrate includes depositing copper (Cu).

11. The method of fabricating an array substrate according to claim 7, wherein forming a transparent conductive layer includes depositing a material selected from a group consisting of indium-tin-oxide (ITO) and indium-zinc-oxide (IZO).

12. The method of fabricating an array substrate according to claim 7, wherein patterning the transparent conductive layer forms pixel electrodes that connect with associated drain electrodes via the drain contact holes.

13. The method of fabricating an array substrate according to claim 7, further including testing the array substrate for opens or shorts.

14. The method of fabricating an array substrate according to claim 13, wherein testing the array substrate for opens or shorts includes applying voltages to the odd gate lines and to the even gate lines.

15. The method of fabricating an array substrate according to claim 14, further including cutting the first pad connectors and the second pad connectors after testing.

16. The method of fabricating an array substrate according to claim 15, further including electrically connecting a tape carrier package the odd gate pads and to the even gate pads.

17. The method of fabricating an array substrate according to claim 16, wherein electrically connecting a tape carrier package to the odd gate pads and to the even gate pads includes contacting the cut first pad connectors and contacting the cut second pad connectors.

18. The method of fabricating an array substrate according to claim 16, wherein electrically connecting a tape carrier package to the odd gate pads and to the even gate pads includes forming an anisotropic conductive film on the cut first pad connectors and on the cut second pad connectors.