Asymmetric data path media access controller

• US 20050105551A1
• Filed: 12/17/2004
• Published: 05/19/2005
• Est. Priority Date: 09/21/2000
• Status: Active Grant

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Tate, Michael
• Granted Patent: US 7,072,997 B2
• Time in Patent Office: Days
• US Class Current: 370/465
• CPC Class Codes: H04L 25/05 Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate

Abstract

A method and apparatus for maintaining data throughput in a data element includes receiving a clock and a first plurality of instances of data having a first width on an input, sampling consecutive ones of instances of the data having the first width at consecutive ones of a first rising edge and a first falling edge of the clock, respectively, to generate two plurality of instances of sampled data having a first width. The plurality of instances of sampled data is then sampled at a second rising edge of the clock and parallelized to generate a second plurality of instances of parallel data having a second width greater than the first width. The parallel data may then be processed to for example generate statistics to monitor link integrity, prior to being transmitted. A 10 Gbps data transmission speed may be maintained using the IEEE 802.3ae-specified media independent interface clock.

Claims

1. A method for maintaining throughput in a data element, comprising the steps of:

receiving in a switch a clock and a plurality of instances of data having a first width on an input, wherein the switch comprises at least one physical layer device, at least one media independent interface, and at least one media access controller;

processing consecutive ones of the plurality of instances of data having the first width to produce more than one of a plurality of instances of data having a second width wherein the second data width are equivalent to the first data width and the more than one of the plurality of instances of data having the second data width are used to produce a plurality of instances of data having a third data width wherein the third data width are greater than the second data width and the plurality of instances of data having the third data width are used to produce a plurality of instances of data having an output data width wherein the output data width are equivalent to the third data width; and

transmitting the plurality of instances of data having the output data width.

2. The method according to claim 1, the processing step further comprising the steps of:

sampling consecutive ones of the plurality of instances of data having the first width at consecutive ones of a first rising edge and a falling edge of the clock;

generating more than one instance of a plurality of data having the second width;

converting the more than one instance of the plurality of data having the second width at a second rising edge of the clock to result in the plurality of instances of data having the third width data;

transmitting a handshake signal; and

transmitting the plurality of instances of data having the third data width.

3. The method according to claim 2, wherein the handshake signal is a pulse.

4. The method according to claims 2, wherein the first and second width data are 32 bits and the third and fourth width data are 64 bits.

5. The method as in claim 2, wherein the clock is received from the at least one media independent interface.

6. The method according to claim 1 wherein the processing step includes a cyclic redundancy check (CRC).

7. The method according to claim 1 wherein the processing step includes statistics generation.

8. The method according to claim 1, wherein the processing step includes a dual data rate sampling.

9. The method according to claim 8 wherein the step of performing dual data rate sampling comprises the steps of, sampling the plurality of instances of data having the first width on the input in accordance with a rising and falling edge of the clock to produce the more than one of the plurality of instances of data having the second width.

10. The method according to claim 9 wherein the first and second width data are 32 bits and the third and fourth width data are 64 bits.

11. The method according to claim 1 wherein the processing step comprises the step of resolving an inter-packet gap.

12. The method according to claim 1 wherein the processing step comprises the step of resolving a preamble detection.

13. The method according to claim 1 wherein the processing step comprises the step of resolving a data alignment.

14. The method according to claim 1 wherein the processing step comprises the step of resolving statistics.

15. The method according to claim 2 wherein the step of transmitting of the plurality of instances of data having the third data width is done after the step of transmitting the handshake signal.

16. The method according to claim 15, wherein the handshake is generated by a first-in-first-out element.

17-45. -45. (canceled)

46. A method for maintaining throughput in a data element, comprising the steps of:

receiving in a switch a first data having first bit-width bits, management bits and clock bits, wherein the switch comprises at least one physical layer device, at least one media independent interface, and at least one media access controller;

inputting the first bit-width bits and clock bits into a receive data path; and

processing the first bit-width bits to generate processed data having a second bit-width which is greater than said first bit-width.

47. The method according to claim 46 wherein the processing step further comprises:

receiving a clock having a clock rate; and

performing dual data rate sampling on the first bit-width data in accordance with said clock to produce the processed data having a second bit-width which is greater than the first bit-width.

48. The method as in claim 47 wherein the step of performing dual data rate sampling on the receive data comprises sampling a first data stream in accordance with a rising and falling edge of the clock.

49. The method as in claim 47, wherein the clock is received from the at least one media independent interface.

50. The method as in claim 47, wherein the step of performing dual data rate sampling on the first bit-width bits comprises inputting the first bit-width bits to two gates, one gate triggering on a rising edge of the clock and the other triggering on a falling edge of the clock.