Electronic device and method of manufacturing the same

• US 20050139882A1
• Filed: 12/30/2004
• Published: 06/30/2005
• Est. Priority Date: 12/30/2003
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Park, Young-soo, Yoo, In-kyeong, Noguchi, Takashi, Xianyu, Wenxu
• Granted Patent: US 7,482,648 B2
• Time in Patent Office: Days
• US Class Current: 257/295
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• CPC Class Codes: H10B 53/30 characterised by the memory core region

Abstract

In an electronic device, and a method of manufacturing the same, the electronic device includes a first substrate, a first lower capacitor on the first substrate, a first lower switching element on the first lower capacitor, and a second substrate on the first lower switching element. The electronic device may further include a second lower switching element which is isolated from the first lower capacitor, and an upper capacitor on the second substrate, the lower electrode of the upper capacitor being connected to the second lower switching element.

Claims

1. A ferroelectric random access memory (FRAM), comprising:

a first substrate;

a first lower capacitor on the first substrate;

a first lower switching element on the first lower capacitor; and

a second substrate on the first lower switching element.

2. The FRAM as claimed in claim 1, wherein the first lower capacitor comprises a first electrode, a ferroelectric layer and a second electrode, which are sequentially stacked on the first substrate, the second electrode being perpendicular to the first electrode.

3. The FRAM as claimed in claim 1, wherein the first lower switching element is a thin film transistor.

4. The FRAM as claimed in claim 1, further comprising a metal line between the first lower capacitor and the first lower switching element, the metal line bonding the first lower capacitor to the first lower switching element.

5. The FRAM as claimed in claim 4, wherein the metal line and the first lower switching element are connected to each other through a conductive plug.

6. The FRAM as claimed in claim 4, further comprising a solder bump between the metal line and the first lower capacitor.

7. The FRAM as claimed in claim 1, further comprising an interlayer insulating layer, the first lower switching element being provided inside the interlayer insulating layer, and a bonding pad on each of the interlayer insulating layer and the first lower capacitor.

8. The FRAM as claimed in claim 1, further comprising a second lower switching element between the first substrate and the second substrate.

9. The FRAM as claimed in claim 8, wherein the first lower capacitor is expanded between the first substrate and the second lower switching element, the first lower capacitor being isolated from the second lower switching element.

10. The FRAM as claimed in claim 8, wherein the first lower switching element is identical to the second lower switching element.

11. The FRAM as claimed in claim 1, further comprising a bit line on the second substrate, the bit line being connected to the first lower switching element.

12. The FRAM as claimed in claim 11, further comprising an upper FRAM on the second substrate.

13. The FRAM as claimed in claim 12, wherein the upper FRAM comprises:

a first upper capacitor having a lower electrode spaced apart from the bit line; and

a first upper switching element stacked on the first upper capacitor.

14. The FRAM as claimed in claim 13, wherein the first upper capacitor is identical to the first lower capacitor.

15. The FRAM as claimed in claim 13, wherein the first upper switching element is identical to the first lower switching element.

16. The FRAM as claimed in claim 13, wherein the bit line is at least two bit lines and wherein the lower electrode of the first upper capacitor is provided on the second substrate between the at least two bit lines.

17. The FRAM as claimed in claim 13, further comprising an interlayer insulating layer between the lower electrode of the first upper capacitor and the second substrate, the interlayer insulating layer covering the bit line.

18. The FRAM as claimed in claim 13, further comprising a metal line between the first upper capacitor and the first upper switching element, the metal line bonding the first upper capacitor to the first upper switching element.

19. The FRAM as claimed in claim 13, further comprising a conductive plug connecting the metal line and the first upper switching element.

20. The FRAM as claimed in claim 13, wherein the first upper switching element is formed inside an interlayer insulating layer, and each of the interlayer insulating layer and the first upper capacitor includes a bonding pad.

21. The FRAM as claimed in claim 13, further comprising a third substrate on the first upper switching element.

22. The FRAM as claimed in claim 21, further comprising a bit line on the third substrate, the bit line being connected to the first upper switching element.

23. The FRAM as claimed in claim 11, further comprising a second lower switching element between the first substrate and the second substrate, the bit line being further connected to the second lower switching element.

24. The FRAM as claimed in claim 23, further comprising a capacitor on the second substrate, the capacitor comprising a lower electrode which is isolated from the bit line and being connected to the second lower switching element.

25. The FRAM as claimed in claim 24, wherein the bit line is at least two bit lines and wherein the lower electrode of the upper capacitor is provided on the second substrate between the at least two bit lines.

26. The FRAM as claimed in claim 24, wherein an area in which the first and second lower switching elements are connected to the bit line has an expanded portion, and the bit line passes over the expanded portion.

27. The FRAM as claimed in claim 24, wherein an area in which the second lower switching element is connected to the upper capacitor has an expanded portion, and the lower electrode passes over the expanded portion.

28. The FRAM as claimed in claim 24, further comprising a protrusion in the bit line, wherein the bit line is connected to the first and second lower switching elements through the protrusion.

29. The FRAM as claimed in claim 24, further comprising a protrusion in the lower electrode of the upper capacitor, wherein the lower electrode is connected to the second lower switching element through the protrusion.

30. The FRAM as claimed in claim 24, wherein the bit line passes over the first and second switching elements and detours around a region in which the lower electrode and the second switching element are connected to each other.

31. The FRAM as claimed in claim 24, further comprising an interlayer insulating layer between the lower electrode of the upper capacitor and the second substrate, the interlayer insulating layer covering the bit line.

32. The FRAM as claimed in claim 31, wherein the lower electrode is parallel to the bit line and passes over the bit line.

33. The FRAM as claimed in claim 24, further comprising an upper FRAM on the upper capacitor, the upper FRAM being isolated from the upper capacitor.

34. The FRAM as claimed in claim 33, wherein the upper FRAM comprises:

a first capacitor; and

a first switching element stacked on the first capacitor.

35. The FRAM as claimed in claim 34, further comprising a third substrate on the first switching element.

36. The FRAM as claimed in claim 35, further comprising:

a second switching element between the third substrate and the first capacitor, the second switching being isolated from the first capacitor;

a bit line on the third substrate and connected to the first and second switching elements; and

a second capacitor on the third substrate and connected to the second switching element, the second capacitor being isolated from the bit line.

37. An electronic device, comprising:

a switching element on a first substrate; and

a functional element on a second substrate and connected to the switching element.

38. The electronic device as claimed in claim 37, wherein the switching element and the functional element are connected to each other through a conductive material.

39. The electronic device as claimed in claim 37, wherein the switching element is a transistor.

40. The electronic device as claimed in claim 37, wherein the functional element is one of a storage medium, a liquid crystal display (LCD), and a transistor.

41. The electronic device as claimed in claim 40, wherein the storage medium is a capacitor or a resistor.

42. The electronic device as claimed in claim 37, wherein the switching element and the functional element are paired and a plurality of pairs of the switching element and the functional element are formed in a stacked structure.

43. The electronic device as claimed in claim 42, wherein the switching element of the stacked structure is provided below the functional element.

44. A method of manufacturing a ferroelectric random access memory (FRAM), comprising:

(a) forming a first capacitor on a first surface of a first substrate;

(b) forming a first switching element on a first surface of a second substrate; and

(c) bonding the first capacitor to the first switching element.

45. The method as claimed in claim 44, wherein forming the first capacitor comprises:

forming a first electrode on the first surface of the first substrate;

forming a ferroelectric layer on the first electrode; and

forming a second electrode on the ferroelectric layer, the second electrode being crossed with the first electrode.

46. The method as claimed in claim 45, further comprising forming a first bonding pad and a first alignment key on the ferroelectric layer.

47. The method as claimed in claim 44, further comprising, between forming the first switching element and bonding the first capacitor to the first switching element:

forming an interlayer insulating layer on the first surface of the second substrate, the interlayer insulating layer covering the first switching element;

forming a via hole in the interlayer insulating layer, the via hole exposing the first switching element;

filling the via hole with a conductive plug; and

forming a metal line on the interlayer insulating layer, the metal line being connected to the conductive plug.

48. The method as claimed in claim 47, wherein forming the via hole comprises forming a second bonding pad and a second alignment key.

49. The method as claimed in claim 44, wherein bonding the first capacitor to the first switching element comprises:

clamping a second surface of the first substrate, the second surface of the first substrate facing the first surface thereof;

clamping a second surface of the second substrate, the second surface of the second substrate facing the first surface thereof;

aligning the first and second substrates to dispose the first capacitor and the first switching element at a bonding position;

pressurizing and contacting the first capacitor and the first switching element;

heating the pressurized and contacted portion of the first capacitor and the first switching element; and

releasing the second surfaces of the first and second substrates.

50. The method as claimed in claim 49, further comprising annealing the pressurized and contacted resultant structure in an ultra high vacuum state, thereby heating the pressurized and contacted portion of the first capacitor and the first switching element.

51. The method as claimed in claim 49, further comprising irradiating the contacted portion of the first capacitor and the first switching element, thereby heating the contacted portion of the first capacitor and the first switching element.

52. The method as claimed in claim 51, further comprising providing a mask between a light source used for irradiating and the second surface of the second substrate, the mask including a light transmitting area, which corresponds to the contacted portion, and a light shielding area which corresponds to other areas.

53. The method as claimed in claim 51, further comprising forming a bit line on the second surface of the second substrate, the bit line being connected to the first switching element.

54. The method as claimed in claim 53, further comprising forming an FRAM layer on the second surface of the second substrate isolated from the bit line.

55. The method as claimed in claim 54, wherein forming the FRAM layer comprises:

forming an upper capacitor on the second face of the second substrate isolated from the bit line; and

forming an upper switching element on the upper capacitor.

56. The method as claimed in claim 55, further comprising an interlayer insulating layer between the upper capacitor and the second surface of the second substrate, the interlayer insulating layer covering the bit line.

57. The method as claimed in claim 55, forming a lower electrode of the upper capacitor on the second surface of the second substrate, the lower electrode being isolated from the bit line.

58. The method as claimed in claim 49, further comprising, after the releasing, thinning at least one of the first substrate and the second substrate.

59. The method as claimed in claim 44, wherein bonding the first capacitor and the first switching element comprises using a solder bump.

60. The method as claimed in claim 44, further comprising forming a second switching element on the first surface of the second substrate.

61. The method as claimed in claim 60, further comprising forming a bit line on the second surface of the second substrate, the bit line being connected to the first and second switching elements.

62. The method as claimed in claim 61, further comprising forming an upper capacitor on the second surface of the second substrate, the upper capacitor being isolated from the bit line and being connected to the second switching element.

63. The method as claimed in claim 62, further comprising forming an interlayer insulating layer between the upper capacitor and the second surface of the second substrate, the interlayer insulating layer covering the bit line.

64. The method as claimed in claim 62, further comprising forming a lower electrode of the upper capacitor on the second surface, the lower electrode being isolated from the bit line.

65. The method as claimed in claim 62, further comprising:

forming an interlayer insulating layer on the upper capacitor; and

forming an FRAM layer on the interlayer insulating layer.

66. The method as claimed in claim 65, wherein forming the FRAM layer comprises:

forming a capacitor on the interlayer insulating layer;

forming a switching element on a first surface of a third substrate; and

bonding the switching element to the capacitor.

67. The method as claimed in claim 65, wherein forming the FRAM layer comprises:

forming a lower capacitor on the interlayer insulating layer;

forming a first switching element to be connected to the lower capacitor and a second switching element to be isolated from the lower capacitor on a first surface of a third substrate;

bonding the first switching element to the lower capacitor;

forming a bit line on a second surface of the third substrate, the second surface of the third substrate facing the first surface thereof, the bit line being connected to the first and second switching elements; and

forming an upper capacitor on the second surface of the third substrate, the upper capacitor being connected to the second switching element, a lower electrode of the upper capacitor being isolated from the bit line.

68. The method as claimed in claim 67, wherein bonding the first switching element to the lower capacitor comprises contacting a metal line connected to the first switching element through a conductive plug to the lower capacitor.

69. A method of manufacturing an electronic device, comprising:

forming a switching element on a first substrate;

forming a functional element on a second substrate; and

bonding the switching element to the functional element.

70. The method as claimed in claim 69, wherein bonding the switching element and the functional element forms a pair, and a plurality of pairs of the switching element and the functional element are further formed on the resultant bonded structure.

71. The method as claimed in claim 70, further comprising:

forming a second switching element using a functional element area of the resultant bonded structure as a substrate;

forming a second functional element on an separate substrate; and

bonding the second functional element to the second switching element.