Semiconductor package

• US 20050139994A1
• Filed: 12/29/2004
• Published: 06/30/2005
• Est. Priority Date: 12/31/2003
• Status: Abandoned Application

• Current Assignee: 931285 Alberta, Ltd., 931289 Alberta, Ltd., Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Lin, Tzu-Bin, Huang, Ya-Ling, Hsu, Hung-Ta
• Application Number:
  US11/023,353
• Publication Number:
  US 20050139994A1
• Time in Patent Office: Days
• US Class Current: 257/706
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/3737 Organic materials with or without a thermoconductive filler
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A semiconductor package includes a die attached to a substrate. Multitudes of conductive structures are conductively connected the die and the substrate. One molding compound encapsulates the die, and thermal interface material is on the molding compound. Next, a heat sink is on the thermal interface material. The mold compound material performs a coefficient of thermal expansion smaller than the heat sink so as to prevent the die or substrate from the damages of internal stresses.

Claims

1. A semiconductor package structure, comprising:

a substrate;

a die attached to said substrate;

a plurality of conductive wires electrically connected to said substrate and said die;

a molding compound encapsulating said die;

a thermal interface material above said molding compound; and

a heat sink on said thermal interface material.

2. The semiconductor package structure according to claim 1, wherein said die is manufactured by a low k copper process.

3. The semiconductor package structure according to claim 1, further comprising a plurality of conductive pads on said die for connecting said conductive wires.

4. The semiconductor package structure according to claim 1, further comprising a plurality of conductive pads on said substrate for connecting said conductive wires.

5. The semiconductor package structure according to claim 1, wherein said molding compound further encapsulates said conductive wires.

6. The semiconductor package structure according to claim 1, wherein said substrate has a plurality of conductive balls on an underside of said substrate.

7. The semiconductor package structure according to claim 6, further comprising said die attached to an upside of said substrate.

8. The semiconductor package structure according to claim 1, wherein said substrate has a signal layer.

9. A semiconductor package structure, comprising:

a substrate having a first surface;

a die having a second and a third surfaces, wherein said second surface is attached to said first surface;

a plurality of conductive wires electrically connected to said first and said third surfaces;

a molding compound encapsulating said die and said conductive wires, wherein said molding compound has a fourth surface;

a thermal interface material above said fourth surface; and

a heat sink on said thermal interface material, wherein said heat sink has a coefficient of thermal expansion bigger than said molding compound.

10. The semiconductor package structure according to claim 9, wherein said heat sink has rigidity bigger than said molding compound.

11. A semiconductor package structure, comprising:

a substrate;

a flip chip attached to said substrate;

a plurality of conductive balls attached and electrically connected to said substrate and said flip chip;

a molding compound encapsulating said flip chip and said conductive balls;

a thermal interface material above said molding compound; and

a heat sink on said thermal interface material.

12. The semiconductor package structure according to claim 11, further comprising a plurality of conductive pads respectively on said substrate and said flip chip for connecting said conductive balls.

13. The semiconductor package structure according to claim 11, wherein said substrate has a plurality of solder balls on an underside of said substrate.

14. The semiconductor package structure according to claim 11, wherein said substrate has a signal layer.