Method and system for transmission control packet (TCP) segmentation offload

• US 20050147126A1
• Filed: 01/06/2004
• Published: 07/07/2005
• Est. Priority Date: 01/06/2004
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Qiu, Jack, Lee, Jonathan
• Granted Patent: US 7,864,806 B2
• Time in Patent Office: Days
• US Class Current: 370/474
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9042 Separate storage for different parts of the packet, e.g. header and payload
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/166 IP fragmentation; TCP segmentation
• CPC Class Codes: H04L 69/326 in the transport layer [OSI layer 4] H04L69/16 takes precedence

Abstract

Certain aspects of the invention for packet segmentation and offload may comprise determining whether an identified packet is a large send offload packet (LSOP). If the identified packet is a LSOP, a selection may be made between a hardware process and a firmware process for handling the LSOP. The LSOP may then be processed by the selected hardware process or firmware process. At least a portion of protocol header information for a first segment of the LSOP may be stored and subsequently utilized for at least a header portion of a second segment of the LSOP. A payload corresponding to the second segment of the LSOP may be placed at a determined offset within a transmit buffer for the second segment. A header portion of the second segment may be updated based on at least a header portion of a previous segment.

Claims

1. A method for packet segmentation and offload, the method comprising:

receiving information identifying at least one packet to be processed;

determining whether an identified packet is a large send offload packet;

if said identified packet is a large send offload packet, selecting between a hardware process and a firmware process for handling said large send offload packet; and

processing said large send offload packet by one of said selected hardware process and said firmware process.

2. The method according to claim 1, further comprising if said identified packet is not a large send offload packet, bypassing said hardware process and said firmware process, and read DMA processing said identified packet from a host memory.

3. The method according to claim 1, further comprising computing at least one checksum for said identified packet in hardware during read DMA processing.

4. The method according to claim 3, further comprising generating in said hardware during said read DMA processing, at least one header for packet segments corresponding to said large send offload packet.

5. The method according to claim 1, further comprising computing at least one checksum for said identified packet in firmware during send data complete processing.

6. The method according to claim 5, further comprising generating in said firmware during said send data complete processing, at least one header for packet segments corresponding to said large send offload packet.

7. The method according to claim 1, further comprising storing at least a portion of protocol header information for a first segment of said large send offload packet.

8. The method according to claim 7, further comprising utilizing at least a portion of said stored protocol header information for at least a header portion of a second segment of said large send offload packet.

9. The method according to claim 8, further comprising placing a payload corresponding to said second segment of said large send offload packet at a determined offset within a transmit buffer for said second segment.

10. The method according to claim 9, further comprising creating a header portion of said second segment based on at least a header portion of a previous segment.

11. A machine-readable storage having stored thereon, a computer program having at least one code section for packet segmentation and offload, the at least one code section being executable by a machine for causing the machine to perform steps comprising:

receiving information identifying at least one packet to be processed;

determining whether an identified packet is a large send offload packet;

if said identified packet is a large send offload packet, selecting between a hardware process and a firmware process for handling said large send offload packet; and

controlling processing of said large send offload packet by one of said selected hardware process and a firmware process.

12. The machine-readable storage according to claim 11, further comprising code for bypassing said hardware process and said firmware process and read DMA processing said identified packet from a host memory, if said identified packet is not a large send offload packet.

13. The machine-readable storage according to claim 11, further comprising code for computing at least one checksum for said identified packet in hardware during read DMA processing.

14. The machine-readable storage according to claim 13, further comprising code for controlling generation in said hardware during said read DMA processing, at least one header for packet segments corresponding to said large send offload packet.

15. The machine-readable storage according to claim 11, further comprising code for computing at least one checksum for said identified packet in firmware during send data complete processing.

16. The machine-readable storage according to claim 15, further comprising code for controlling generation in said firmware during said send data complete processing, at least one header for packet segments corresponding to said large send offload packet.

17. The machine-readable storage according to claim 11, further comprising code for storing at least a portion of protocol header information for a first segment of said large send offload packet.

18. The machine-readable storage according to claim 17, further comprising code for utilizing at least a portion of said stored protocol header information for at least a header portion of a second segment of said large send offload packet.

19. The machine-readable storage according to claim 18, further comprising code for placing a payload corresponding to said second segment of said large send offload packet at a determined offset within a transmit buffer for said second segment.

20. The machine-readable storage according to claim 19, further comprising code for creating a header portion of said second segment based on at least a header portion of a previous segment.

21. A system for packet segmentation and offload, the system comprising:

a send data initiator that receives information identifying at least one packet to be processed;

at least one of an internal CPU and said send data initiator determines whether an identified packet is a large send offload packet;

at least one selector that selects between a hardware process and a firmware process for handling said large send offload packet if said identified packet is a large send offload packet; and

at least one processor that processes said large send offload packet by one of said selected hardware process and said firmware process.

22. The system according to claim 21, wherein said at least one selector further allows bypassing of said hardware process and said firmware process, and said at least one processor read DMA processes said identified packet from a host memory if said identified packet is not a send offload packet.

23. The system according to claim 21, wherein said at least one processor computes at least one checksum for said identified packet in hardware during read DMA processing.

24. The system according to claim 23, wherein said at least one processor generates in said hardware during said read DMA processing, at least one header for packet segments corresponding to said large send offload packet.

25. The system according to claim 21, wherein said at least one processor computes at least one checksum for said identified packet in firmware during send data complete processing.

26. The system according to claim 25, wherein said at least one processor generates in said firmware during said send data complete processing, at least one header for packet segments corresponding to said large send offload packet.

27. The system according to claim 21, wherein said at least one processor stores at least a portion of protocol header information for a first segment of said large send offload packet.

28. The system according to claim 27, wherein said at least one processor utilizes at least a portion of said stored protocol header information for at least a header portion of a second segment of said large send offload packet.

29. The system according to claim 28, wherein said at least one processor places a payload corresponding to said second segment of said large send offload packet at a determined offset within a transmit buffer for said second segment.

30. The system according to claim 29, wherein said at least one processor creates a header portion of said second segment based on at least a header portion of a previous segment.

31. The system according to claim 21, wherein said at least one processor comprises at least one of a read DMA engine, a read DMA post-processor, an internal CPU and a send data complete module.

32. A system for packet segmentation and offload, the system comprising:

a read DMA processor;

a memory arbiter coupled to said read DMA processor;

a transmit buffer memory coupled to said read DMA processor;

a send data initiator coupled to said read DMA processor;

a send data complete module coupled to said read DMA processor; and

a bus interface coupled to said read DMA processor.

33. The system according to claim 32, wherein said bus interface is at least one of a PCI, PCI-X and PCI Express bus interface.

34. The system according to claim 32, further comprising an internal CPU coupled to said read DMA processor;

35. The system according to claim 34, wherein said read DMA processor, said internal CPU, said memory arbiter, said transmit buffer memory, said send data initiator, said send data complete module and said bus interface are integrated within a single chip.

36. The system according to claim 34, wherein said read DMA processor, said internal CPU, said memory arbiter, said transmit buffer memory, said send data initiator, said send data complete module and said bus interface are integrated within a network interface card.

37. The system according to claim 32, wherein a host system is coupled to said bus interface.