Bandwidth efficient coded modulation scheme based on MLC (multi-level code) signals having multiple maps

• US 20050149843A1
• Filed: 12/20/2004
• Published: 07/07/2005
• Est. Priority Date: 05/31/2002
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Shen, Ba-Zhong, Tran, Hau Thien, Cameron, Kelly Brian
• Granted Patent: US 7,197,690 B2
• Time in Patent Office: Days
• US Class Current: 714/800
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/1105 Decoding
• CPC Class Codes: H03M 13/1111 Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
• CPC Class Codes: H03M 13/1148 Structural properties of the code parity-check or generator matrix
• CPC Class Codes: H03M 13/1177 Regular LDPC codes with parity-check matrices wherein all rows and columns have the same row weight and column weight, respectively
• CPC Class Codes: H03M 13/255 with Low Density Parity Check [LDPC] codes
• CPC Class Codes: H03M 13/256 with trellis coding, e.g. with convolutional codes and TCM
• CPC Class Codes: H03M 13/258 with turbo codes, e.g. Turbo Trellis Coded Modulation [TTCM]
• CPC Class Codes: H03M 13/2957 Turbo codes and decoding
• CPC Class Codes: H03M 13/4161 implementing path management
• CPC Class Codes: H03M 13/45 Soft decoding, i.e. using symbol reliability information H03M13/41 takes precedence
• CPC Class Codes: H03M 13/6561 Parallelized implementations
• CPC Class Codes: H03M 5/20 the pulses having more than three levels
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/005 Iterative decoding, including iteration between signal detection and decoding operation
• CPC Class Codes: H04L 1/0058 Block-coded modulation
• CPC Class Codes: H04L 1/006 Trellis-coded modulation
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 27/18 Phase-modulated carrier systems, i.e. using phase-shift keying H04L27/32 takes precedence
• CPC Class Codes: H04L 27/183 Multiresolution systems
• CPC Class Codes: H04L 27/186 : in which the information is carried by both the individual signal points and the subset to which the individual signal points belong, e.g. coset coding or related schemes
• CPC Class Codes: H04L 27/2053 : using more than one carrier, e.g. carriers with different phases

Abstract

Bandwidth efficient coded modulation scheme based on MLC (Multi-Level Code) signals having multiple maps. The use of multiple maps is adapted to various types of coded signals including multi-level LDPC coded modulation signals and other MLC signals to provide for a significant performance gain in the continual effort trying to reach towards Shannon'"'"'s limit. In the instance of LDPC coded signals, various level LDPC codewords are generated from individual corresponding LDPC encoders. These various level LDPC codewords are arranged into a number of sub-blocks. Encoded bits from multiple level LDPC codewords within each of the sub-blocks are arranged to form symbols that are mapped according to at least two modulations. Each modulation includes a constellation shape and a corresponding mapping. This use of multiple mappings provides for improved performance when compared to encoders that employ only a single mapping.

Claims

1. An encoder that is operable to generate an MLC LDPC (Multi-Level Code Low Density Parity Check) coded modulation signal that is mapped using a plurality of mappings, the encoder comprising:

a data partitioner that is operable to partition a plurality of input bits into a first plurality of input bits and a second plurality of input bits;

a first LDPC (Low Density Parity Check) encoder that is operable to encode the first plurality of input bits thereby generating a first level LDPC codeword;

a second LDPC encoder that is operable to encode the second plurality of input bits thereby generating a second level LDPC codeword;

a symbol mapper that is operable to;

group at least a first bit of the first level LDPC codeword and at least a first bit of the second level LDPC codeword thereby forming a first sub-block symbol of a plurality of sub-block symbols;

group at least a second bit of the first level LDPC codeword and at least a second bit of the second level LDPC codeword thereby forming a second sub-block symbol of the plurality of sub-block symbols;

symbol map the first sub-block symbol of the plurality of sub-block symbols according to a first modulation that includes a first constellation shape and a corresponding first mapping of the plurality of mappings; and

symbol map the second sub-block symbol of the plurality of sub-block symbols according to a second modulation that includes a second constellation shape and a corresponding second mapping of the plurality of mappings.

2. The encoder of claim 1, wherein:

at least one of the corresponding first mapping of the plurality of mappings and the corresponding second mapping of the plurality of mappings is a Gray code mapping.

3. The encoder of claim 1, wherein:

the first LDPC encoder is operable to encode the first plurality of input bits using a first code rate LDPC code thereby generating the first level LDPC codeword; and

the second LDPC encoder is operable to encode the second plurality of input bits using a second code rate LDPC code thereby generating the second level LDPC codeword.

4. The encoder of claim 3, wherein:

at least one of the first code rate LDPC code and the second code rate LDPC code is an irregular LDPC code.

5. The encoder of claim 3, wherein:

at least one of the first code rate LDPC code and the second code rate LDPC code is a regular LDPC code.

6. The encoder of claim 3, wherein:

the MLC LDPC coded modulation signal has an MLC LDPC code rate that is a sum of a first code rate of the first code rate LDPC code and a second code rate of the second code rate LDPC code.

7. The encoder of claim 1, further comprising a clock counter and a map selector wherein:

the clock counter is operable to provide a clock signal having clock cycles;

the map selector is operable to;

receive the clock signal from the clock counter;

provide a first selected mapping to the symbol mapper during a first clock cycle of the clock signal;

provide a second selected mapping to the symbol mapper during a second clock cycle of the clock signal; and

the symbol mapper is operable to employ at least one of the first selected mapping and the second selected mapping as at least one of the first mapping of the plurality of mappings and the second mapping of the plurality of mappings.

8. The encoder of claim 1, wherein:

the symbol mapper is operable to;

symbol map the first sub-block symbol of the plurality of sub-block symbols according to the first modulation that includes the first constellation shape and the corresponding first mapping of the plurality of mappings during a first clock cycle of a clock signal; and

symbol map the second sub-block symbol of the plurality of sub-block symbols according to the second modulation that includes the second constellation shape and the corresponding second mapping of the plurality of mappings during a second clock cycle of a clock signal.

9. The encoder of claim 1, wherein:

the first LDPC encoder is operable to encode the first plurality of input bits using a code rate ½

LDPC code thereby generating the first level LDPC codeword; and

the second LDPC encoder is operable to encode the second plurality of input bits using a code rate ¾

LDPC code thereby generating the second level LDPC codeword.

10. The encoder of claim 1, wherein:

the first level LDPC codeword and the second level LDPC codeword form a block;

the block is evenly divided into a plurality of sub-blocks;

the first sub-block symbol of the plurality of sub-block symbols is included within a first sub-block of the plurality of sub-blocks; and

the second sub-block symbol of the plurality of sub-block symbols is included within the second sub-block of the plurality of sub-blocks.

11. The encoder of claim 1, wherein:

the first constellation shape is an 8 PSK (Phase Shift Key) constellation shape; and

the second constellation shape is the 8 PSK constellation shape.

12. An encoder that is operable to generate an MLC LDPC (Multi-Level Code Low Density Parity Check) coded modulation signal that is mapped using a plurality of mappings, the encoder comprising:

a data partitioner that is operable to partition a plurality of input bits into a first plurality of input bits and a second plurality of input bits;

a first LDPC (Low Density Parity Check) encoder that is operable to encode the first plurality of input bits using a first code rate LDPC code thereby generating a first level LDPC codeword;

a second LDPC encoder that is operable to encode the second plurality of input bits using a second code rate LDPC code thereby generating a second level LDPC codeword;

a symbol mapper that is operable to;

group at least a first bit of the first level LDPC codeword and at least a first bit of the second level LDPC codeword thereby forming a first sub-block symbol of a plurality of sub-block symbols;

group at least a second bit of the first level LDPC codeword and at least a second bit of the second level LDPC codeword thereby forming a second sub-block symbol of the plurality of sub-block symbols;

symbol map the first sub-block symbol of the plurality of sub-block symbols according to a first modulation that includes a first constellation shape and a corresponding first mapping of the plurality of mappings;

symbol map the second sub-block symbol of the plurality of sub-block symbols according to a second modulation that includes a second constellation shape and a corresponding second mapping of the plurality of mappings;

a clock counter that is operable to provide a clock signal having clock cycles;

a map selector that is operable to;

receive the clock signal from the clock counter;

provide a first selected mapping to the symbol mapper during a first clock cycle of the clock signal;

provide a second selected mapping to the symbol mapper during a second clock cycle of the clock signal; and

wherein the symbol mapper is operable to employ at least one of the first selected mapping and the second selected mapping as at least one of the first mapping of the plurality of mappings and the second mapping of the plurality of mappings.

13. A method for generating an MLC LDPC (Multi-Level Code Low Density Parity Check) coded modulation signal that is mapped using a plurality of mappings, the method comprising:

partitioning a plurality of input bits into a first plurality of input bits and a second plurality of input bits;

encoding the first plurality of input bits thereby generating a first level LDPC codeword;

encoding the second plurality of input bits thereby generating a second level LDPC codeword;

grouping at least a first bit of the first level LDPC codeword and at least a first bit of the second level LDPC codeword thereby forming a first sub-block symbol of a plurality of sub-block symbols;

grouping at least a second bit of the first level LDPC codeword and at least a second bit of the second level LDPC codeword thereby forming a second sub-block symbol of the plurality of sub-block symbols;

symbol mapping the first sub-block symbol of the plurality of sub-block symbols according to a first modulation that includes a first constellation shape and a corresponding first mapping of the plurality of mappings; and

symbol mapping the second sub-block symbol of the plurality of sub-block symbols according to a second modulation that includes a second constellation shape and a corresponding second mapping of the plurality of mappings.

14. The method of claim 13, wherein:

at least one of the corresponding first mapping of the plurality of mappings and the corresponding second mapping of the plurality of mappings is a Gray code mapping.

15. The method of claim 13, further comprising:

encoding the first plurality of input bits using a first code rate LDPC code thereby generating the first level LDPC codeword; and

encoding the second plurality of input bits using a second code rate LDPC code thereby generating the second level LDPC codeword.

16. The method of claim 15, wherein:

at least one of the first code rate LDPC code and the second code rate LDPC code is an irregular LDPC code.

17. The method of claim 15, wherein:

at least one of the first code rate LDPC code and the second code rate LDPC code is a regular LDPC code.

18. The method of claim 15, wherein:

the MLC LDPC coded modulation signal has an MLC LDPC code rate that is a sum of a first code rate of the first code rate LDPC code and a second code rate of the second code rate LDPC code.

19. The method of claim 13, further comprising:

providing a clock signal having clock cycles;

providing a first selected mapping during a first clock cycle of the clock signal;

providing a second selected mapping during a second clock cycle of the clock signal; and

employing at least one of the first selected mapping and the second selected mapping as at least one of the first mapping of the plurality of mappings and the second mapping of the plurality of mappings.

20. The method of claim 13, further comprising:

symbol mapping the first sub-block symbol of the plurality of sub-block symbols according to the first modulation that includes the first constellation shape and the corresponding first mapping of the plurality of mappings during a first clock cycle of a clock signal; and

symbol mapping the second sub-block symbol of the plurality of sub-block symbols according to the second modulation that includes the second constellation shape and the corresponding second mapping of the plurality of mappings during a second clock cycle of a clock signal.

21. The method of claim 13, further comprising:

encoding the first plurality of input bits using a code rate ½

LDPC code thereby generating the first level LDPC codeword; and

encoding the second plurality of input bits using a code rate ¾

LDPC code thereby generating the second level LDPC codeword.

22. The method of claim 13, further comprising:

forming a block with the first level LDPC codeword and the second level LDPC codeword;

evenly dividing the block into a plurality of sub-blocks;

including the first sub-block symbol of the plurality of sub-block symbols within a first sub-block of the plurality of sub-blocks; and

including the second sub-block symbol of the plurality of sub-block symbols within the second sub-block of the plurality of sub-blocks.

23. The method of claim 13, wherein:

the first constellation shape is an 8 PSK (Phase Shift Key) constellation shape; and

the second constellation shape is the 8 PSK constellation shape.