DISCRIMINATIVE SOI WITH OXIDE HOLES UNDERNEATH DC SOURCE/DRAIN

• US 20050151193A1
• Filed: 01/08/2004
• Published: 07/14/2005
• Est. Priority Date: 01/08/2004
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Wong, Robert C.
• Granted Patent: US 6,958,516 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence

Abstract

A selective SOI structure having body contacts for all the devices while excluding the buried oxide that is directly underneath diffusions of DC nodes such as applied voltage Vdd, ground GND, reference voltage Vref, and other like DC nodes is provided. The selective SOI structure of the present invention can be used in ICs to enhance the performance of the circuit. The selective SOI structure of the present invention includes a silicon-on-insulator (SOI) substrate material comprising a top Si-containing layer having a plurality of SOI devices located thereon. The SOI devices are in contact with an underlying Si-containing substrate via a body contact region. A DC node diffusion region not containing an underlying buried oxide region is adjacent to one of the SOI devices.

Claims

1. A selective silicon-on-insulator (SOI) structure comprising:

a silicon-on-insulator (SOI) substrate material comprising a top Si-containing layer having a plurality of SOI devices located thereon, said SOI devices are in contact with an underlying Si-containing substrate via a body contact region; and

a DC node diffusion region adjacent to one of said SOI devices, said DC node diffusion region is located within bulk silicon without oxide underneath thereby the DC node diffusion region is in contact with said Si-containing substrate.

2. The selective SOI structure of claim 1 wherein said plurality of SOI devices comprise metal oxide semiconductor field effect transistors (MOSFETs).

3. The selective SOI structure of claim 1 wherein said plurality of SOI devices are located atop a top Si-containing layer of said SOI substrate material.

4. The selective SOI structure of claim 3 wherein said plurality of SOI devices comprising active source/drain regions located with said top Si-containing layer.

5. The selective SOI structure of claim 4 wherein said active source/drain regions are located atop a buried oxide.

6. The selective SOI structure of claim 5 wherein said buried oxide is a lateral etched area located adjacent to a trench isolation region.

7. Thee selective SOI structure of claim 1 wherein said DC node diffusion region comprises a region in which a source voltage can be applied, a region in which a reference voltage can be applied, a ground region or any combination.

9. The selective SOI structure of claim 2 wherein the MOSFETs comprise a gate dielectric and a gate conductor.

10. The selective SOI structure of claim 1 wherein said SOI substrate is an additive SOI substrate having discriminative regions for forming said DC node diffusion region.

11. The selective SOI structure of claim 1 wherein said SOI substrate is comprised of a Si-containing material.

12. The selective SOI structure of claim 11 wherein said Si-containing material is selected from the group consisting of Si, SiGe, SiC, SiGeC, Si/Si, Si/SiC, and Si/SiGeC

13. The selective SOI structure of claim 3 wherein said top Si-containing layer has a thickness from about 50 to about 200 nm.

8. (canceled)

14. An integrated circuit comprising at least one selective silicon-on-insulator (SOI) structure said at least one selective SOI structure comprising a silicon-on-insulator (SO) substrate material comprising a top Si-containing layer having a plurality of SOI devices located thereon, said SOI devices are in contact with an underlying Si-containing substrate via a body contact region;

and a DC node diffusion region adjacent to one of said SOI devices, said DC node diffusion region is located within bulk silicon without oxide underneath thereby the DC node diffusion region is in contact with said Si-containing substrate.

15. A semiconductor substrate comprising:

an SOI substrate;

a DC node diffusion region in said SOI substrate; and

a buried oxide material within said SOI substrate, wherein said DC node diffusion region is located within bulk silicon without oxide underneath thereby the DC node diffusion region is in contact with an underlying Si-containing substrate of said SOI substrate.

16. The semiconductor substrate of claim 15 wherein said SOI substrate includes a top Si-containing layer.

17. The semiconductor substrate of claim 16 wherein the top Si-containing layer and the underlying Si-containing substrate are composed of a silicon semiconductor material selected from the group consisting of Si, SiGe, SiC, SiGeC, Si/Si, Si/SiC, and Si/SiGeC

18. The semiconductor substrate of claim 16 wherein said top Si-containing layer has a thickness from about 50 to about 200 nm.

19. The semiconductor substrate of claim 15 wherein the buried oxide material is crystalline.

20. The semiconductor substrate of claim 15 wherein the buried oxide material is non-crystalline.

21. The semiconductor substrate of claim 15 wherein the buried oxide material has a thickness from about 30 to about 100 nm.

22. The semiconductor substrate of claim 15 further comprising at least one trench isolation region that is in contact with said buried oxide material.

23. The semiconductor substrate of claim 15 wherein said DC node diffusion region comprises a region in which a source voltage can be applied, a region in which a reference voltage can be applied, a ground region or any combination.

24. (canceled)