Multilayer wiring board including stacked via structure

• US 20050155791A1
• Filed: 05/17/2004
• Published: 07/21/2005
• Est. Priority Date: 05/16/2003
• Status: Active Grant

• Current Assignee: NGK Spark PLUG Company Limited
• Original Assignee: NGK Spark PLUG Company Limited
• Inventors: Saiki, Hajime
• Granted Patent: US 7,164,085 B2
• Time in Patent Office: Days
• US Class Current: 174/262
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15312 being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H05K 1/112 directly combined with via connections
• CPC Class Codes: H05K 2201/0347 Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias reinforcing the conductive pattern H05K3/24
• CPC Class Codes: H05K 2201/09563 Metal filled via plated through-hole filled with insulating material H05K2201/0959
• CPC Class Codes: H05K 2201/0959 Plated through-holes or plated blind vias filled with insulating material
• CPC Class Codes: H05K 2201/096 Vertically aligned vias, holes or stacked vias
• CPC Class Codes: H05K 2201/10318 Surface mounted metallic pins
• CPC Class Codes: H05K 2201/10636 Leadless chip, e.g. chip capacitor or resistor
• CPC Class Codes: H05K 3/4602 characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A multilayer wiring board includes a substrate, a first planar conductor layer, a second planar conductor layer, resin dielectric layers, filled vias, and stacked via structures. Each of the stacked via structures is disposed in the resin dielectric layers and is configured such that the filled vias are stacked substantially coaxially and are mutually connected together. A first end of the stacked via structure is connected directly to either the first planar conductor layer or the second planar conductor layer. A second end of the stacked via structure is unconnected, directly, to both the first planar conductor layer and the second planar conductor layer.

Claims

1. A multilayer wiring board comprising:

a substrate having a first main surface and a second main surface;

a first planar conductor layer disposed, directly or indirectly, on at least one of the first main surface and the second main surface;

a second planar conductor layer disposed in spaced relation to the first planar conductor layer;

a plurality of resin dielectric layers interposed between the first planar conductor layer and the second planar conductor layer;

filled vias formed in the resin dielectric layers; and

a stacked via structure disposed in the resin dielectric layers and comprising a plurality of the filled vias stacked substantially coaxially and mutually connected together;

the stacked via structure having a first end and a second end;

the first end being directly connected to either the first planar conductor layer or the second planar conductor layer; and

the second end being unconnected, directly, to the first planar conductor layer and being unconnected, directly, to the second planar conductor layer.

2. A multilayer wiring board comprising:

a substrate having a first main surface and a second main surface;

a first planar conductor layer disposed, directly or indirectly, on at least one of the first main surface and the second main surface;

a second planar conductor layer disposed in spaced relation to the first planar conductor layer;

resin dielectric layers interposed between the first planar conductor layer and the second planar conductor layer;

filled vias formed in the resin dielectric layers; and

a stacked via structure disposed in the resin dielectric layers and comprising a plurality of the filled vias stacked substantially coaxially and mutually connected together;

the stacked via structure having a first end and a second end;

the first end being connected directly to the second planar conductor layer; and

the second end being located away from the first planar conductor layer.

3. A multilayer wiring board comprising:

a substrate having a first main surface and a second main surface;

a first planar conductor layer disposed, directly or indirectly, on at least one of the first main surface and the second main surface;

a second planar conductor layer disposed in spaced relation to the first planar conductor layer;

resin dielectric layers interposed between the first planar conductor layer and the second planar conductor layer;

filled vias formed in the resin dielectric layers;

a stacked via structure disposed in the resin dielectric layers and comprising a plurality of the filled vias stacked substantially coaxially and mutually connected together; and

a conformal via formed in one of the resin dielectric layers and having a land portion smaller in area than the first and second planar conductor layers;

the stacked via structure having a first end and a second end;

the first end being connected directly to the second planar conductor layer;

the second end being connected directly to the land portion of the conformal via; and

a bottom surface of the conformal via being connected directly to the first planar conductor layer.

4. A multilayer wiring board comprising:

a substrate having a first main surface and a second main surface;

a first planar conductor layer disposed, directly or indirectly, on at least one of the first main surface and the second main surface;

a second planar conductor layer disposed in spaced relation to the first planar conductor layer;

resin dielectric layers interposed between the first planar conductor layer and the second planar conductor layer;

filled vias formed in the resin dielectric layers;

a stacked via structure disposed in the resin dielectric layers and comprising a plurality of the filled vias stacked substantially coaxially and mutually connected together; and

a further filled via formed in one of the resin dielectric layers and having a land portion smaller in area than the first and second planar conductor layers;

the stacked via structure having a first end and a second end;

the first end being connected directly to the second planar conductor layer;

the second end being connected directly to the land portion of the further filled via; and

a bottom surface of the further filled via being connected directly to the first planar conductor layer.