Method for fabricating an array substrate for in-plane switching liquid crystal display device having multi-domain

• US 20050157239A1
• Filed: 03/17/2005
• Published: 07/21/2005
• Est. Priority Date: 07/27/2001
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Yoo, Jang-Jin
• Granted Patent: US 7,092,060 B2
• Time in Patent Office: Days
• US Class Current: 349/141
• CPC Class Codes: G02F 1/133707 Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]

Abstract

A method for fabricating an array substrate for an in-plane switching liquid crystal display device includes forming a gate line and a data line on the substrate, the gate line and the data line crossing each other to define a pixel region, forming a thin film transistor that is electrically connected to the gate and data lines, and forming a common line parallel to the gate line. A plurality of common electrodes are formed to perpendicularly extend from the common line. A plurality of pixel electrodes are formed in an alternating pattern with the plurality of common electrodes, and an overcoat layer is formed over the plurality of common electrodes and the plurality of pixel electrodes, the overcoat layer having a plurality of holes.

Claims

1-20. -20. (canceled)

21. A method for fabricating an array substrate for an in-plane switching liquid crystal display device, comprising:

forming a gate line and a data line on a substrate, the gate line and the data line crossing each other to define a pixel region;

forming a thin film transistor on the substrate, the thin film transistor being electrically connected to the gate and data lines;

forming a plurality of common electrodes perpendicularly extended from the common line;

forming a gate insulator over the plurality of common electrodes;

forming a plurality of pixel electrodes on the gate insulator, wherein the plurality of pixel electrodes form an alternating pattern with the plurality of common electrodes; and

forming an overcoat layer over the plurality of common and pixel electrodes, the overcoat layer having a plurality of holes.

22. The method according to claim 21, further comprising forming a liquid crystal layer over the overcoat layer, the overcoat layer having a smaller dielectric constant than the liquid crystal layer.

23. The method according to claim 22, wherein each hole is formed in a shape of one of a circle, a triangle, a quadrangle, and a hexagon.

24. The method according to claim 21, wherein the plurality of holes are formed between each of the plurality of common electrodes or each of the plurality of pixel electrodes.

25. The method according to claim 24, wherein the plurality of holes have a length along a first direction and a width, the first direction being inclined with respect to the plurality of common and pixel electrodes.

26. The method according to claim 25, wherein the plurality of holes between each of the pixel electrodes are formed substantially symmetric with respect to each other.

27. The method according to claim 21, further comprising forming a liquid crystal layer over the overcoat layer, the liquid crystal layer having one of positive dielectric anisotropy and negative dielectric anisotropy.

28. The method according to claim 21, wherein the overcoat layer is formed of one of benzocyclobutene and acrylic resin.

29. The method according to claim 21, wherein the plurality of holes are formed over the plurality of common and pixel electrodes.

30. The method according to claim 29, wherein the plurality of holes over the plurality of common electrodes form a firs line and the plurality of holes over the plurality of pixel electrodes form a second line.

31. The method according to claim 30, wherein the plurality of holes of the first line are spaced apart from the plurality of holes of the second line.

32. The method according to claim 21, further comprising forming a gate insulator on the plurality of common electrodes.

33. The method according to claim 32, wherein the plurality of holes expose a portion of the gate insulator.

34. A method for fabricating an array substrate for an in-plane switching mode liquid crystal display device, comprising:

forming a gate line and a data line an a substrate, the gate line and the data line crossing each other to define a pixel region;

forming a thin film transistor on the substrate, the thin film transistor being electrically connected to the gate and data lines;

forming a common line parallel to the gate line;

forming a plurality of common electrodes parallel to the common line, the plurality of common electrodes being electrically connected to the common line;

forming a plurality of pixel electrodes on the substrate in an alternating pattern with the plurality of common electrodes; and

forming an overcoat layer over the plurality of common and pixel electrodes, the overcoat layer having a plurality of holes.

35. The method according to claim 34, further comprising forming a liquid crystal layer over the overcoat layer, the overcoat layer having a smaller dielectric constant than the liquid crystal layer.

36. The method according to claim 34, wherein each hole is formed in a shape of one of a circle, a triangle, a quadrangle, and a hexagon.

37. The method according to claim 34, wherein the plurality of holes are formed between each of the plurality of common or each of the plurality of pixel electrodes.

38. The method according to claim 37, wherein the plurality of holes have a length along a first direction and a width, the first direction being inclined with respect to the plurality of common and pixel electrodes.

39. The method according to claim 38, wherein the plurality of holes between each of the pixel electrodes are formed substantially symmetric with respect to each other the plurality of common and pixel electrodes.

40. The method according to claim 34, further comprising forming a liquid crystal layer over the overcoat layer, the liquid crystal layer having one of positive dielectric anisotropy and negative dielectric anisotropy.

41. The method according to claim 34, wherein the overcoat layer is made of one of benzocyclobutene and acrylic resin.

42. The method according to claim 34, wherein the plurality of holes are formed over the plurality of common and pixel electrodes.

43. The method according to claim 42, wherein the plurality of holes over the plurality of common electrodes form a first line and the plurality of holes over the plurality of pixel electrodes form a second line.

44. The method according to claim 43, wherein the plurality of holes of the first line are spaced apart from the plurality of holes of the second line.

45. The method according to claim 34, further comprising forming a gate insulator on the plurality of common electrodes.

46. The method according to claim 34, wherein the plurality of holes expose a portion of the gate insulator.