Mechanism for reducing write problems by controlling charge pumps for flash memory

• US 20050160316A1
• Filed: 12/02/2003
• Published: 07/21/2005
• Est. Priority Date: 12/02/2002
• Status: Active Grant

• Current Assignee: Memjet Technology Ltd. (Memjet Limited)
• Original Assignee: Silverbrook Research Pty Limited
• Inventors: Shipton, Gary
• Granted Patent: US 7,278,034 B2
• Time in Patent Office: Days
• US Class Current: 714/22
• CPC Class Codes: B41J 2/04505 aiming at correcting alignment
• CPC Class Codes: B41J 2/04508 aiming at correcting other parameters
• CPC Class Codes: B41J 2/0451 for detecting failure, e.g. clogging, malfunctioning actuator
• CPC Class Codes: B41J 2/04528 aiming at warming up the head
• CPC Class Codes: B41J 2/04541 Specific driving circuit
• CPC Class Codes: B41J 2/04543 Block driving
• CPC Class Codes: B41J 2/04563 detecting head temperature; Ink temperature
• CPC Class Codes: B41J 2/04573 Timing; Delays
• CPC Class Codes: B41J 2/04586 controlling heads of a type not covered by groups B41J2/04575 - B41J2/04585, or of an undefined type
• CPC Class Codes: B41J 2202/20 Modules
• CPC Class Codes: G06F 21/554 involving event detection and direct action
• CPC Class Codes: G06F 21/57 Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
• CPC Class Codes: G06F 21/575 Secure boot
• CPC Class Codes: G06F 21/64 Protecting data integrity, e.g. using checksums, certificates or signatures
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers
• CPC Class Codes: G06F 21/74 operating in dual or compartmented mode, i.e. at least one secure mode
• CPC Class Codes: G06F 21/78 to assure secure storage of data address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00
• CPC Class Codes: H03K 5/1252 Suppression or limitation of noise or interference specially adapted for transmission systems H04B15/00, H04L25/08
• CPC Class Codes: H04N 1/405 Halftoning, i.e. converting the picture signal of a continuous-tone original into a corresponding signal showing only two levels
• CPC Class Codes: Y10S 707/99933 : Query processing, i.e. searching
• CPC Class Codes: Y10S 707/99939 : Privileged access
• CPC Class Codes: Y10T 29/49401 : Fluid pattern dispersing device making, e.g., ink jet

Abstract

An integrated circuit comprising a processor, a memory that the processor can access, a memory access unit for controlling accesses to the memory, an input for receiving power for the integrated circuit from an external power source, and a power detection unit, the power detection unit being configured to: monitor a quality of power supplied to the input; and in the event the quality of the power drops below a predetermined threshold, disabling a power supply to circuitry for use in writing to the memory, such that the memory access unit'"'"'s ability to alter data in the memory is disabled prior to address or data values to be written to the memory becoming unreliable due to failing power.

Claims

1. An integrated circuit comprising a processor, a memory that the processor can access, a memory access unit for controlling accesses to the memory, an input for receiving power for the integrated circuit from an external power source, and a power detection unit, the power detection unit being configured to:

monitor a quality of power supplied to the input;

in the event the quality of the power drops below a predetermined threshold, disabling a power supply to circuitry for use in writing to the memory, such that the memory access unit'"'"'s ability to alter data in the memory is disabled prior to address or data values to be written to the memory becoming unreliable due to failing power.

2. An integrated circuit according to claim 1, wherein the memory is flash memory and the power supply is one or more charge pump circuits.

3. An integrated circuit according to claim 2, wherein a voltage output by the power supply falls fast enough that the voltage supplied to the flash memory becomes too low to enable a change in contents of the flash memory before the voltage levels of the address or data values become invalid.

4. An integrated circuit according to claim 1, configured to cause a reset of at least some of the circuitry on the integrated circuit following disabling of the power supply.

5. An integrated circuit according to claim 4, programmed or designed to have a variable delay between disabling of the power supply and causing the reset.