IPHD (iterative parallel hybrid decoding) of various MLC (multi-level code) signals
First Claim
1. A decoder that is operable to perform IPHD (Iterative Parallel Hybrid Decoding) on a MLC (Multi-Level Code) LDPC (Low Density Parity Check) signal, the decoder comprising:
- an initialize edge message functional block that is operable to;
receive I, Q (In-phase, Quadrature) values corresponding to a symbol of the MLC LDPC signal; and
initialize a plurality of edge messages with respect to a plurality of bit nodes to a plurality of predetermined values for each level of the MLC LDPC signal;
a plurality of check engines in a parallel arrangement that includes a separate check engine that corresponds to each level of the MLC LDPC signal that is operable to;
for each level of the MLC LDPC signal, the corresponding check engine of the plurality of check engines is operable to receive the initialized plurality of edge messages with respect to a plurality of bit nodes from the initialize edge message functional block; and
for each level of the MLC LDPC signal, the corresponding check engine of the plurality of check engines is operable to perform check node processing that involves updating a plurality of edge messages with respect to a plurality of check nodes;
a symbol update engine that is operable to;
for each level of the MLC LDPC signal, receive the updated plurality of edge messages with respect to the plurality of check nodes from the plurality of check engines;
receive the I, Q values corresponding to the symbol of the MLC LDPC signal;
calculate a plurality of symbol metrics using the I, Q values;
calculate a plurality of LLR (Log-Likelihood Ratio) bit metrics using the plurality of symbol metrics;
calculate a plurality of logarithms of probabilities of bits of the symbol of the MLC LDPC signal using the plurality of LLR bit metrics and the updated pluralities of edge messages with respect to the plurality of check nodes corresponding to all levels of the MLC LDPC signal; and
estimate a logarithm of a probability of the symbol of the MLC LDPC signal using the plurality of logarithms of probabilities of bits of the symbol of the MLC LDPC signal using and at least one symbol metric of the plurality of symbol metrics; and
a plurality of bit engines in a parallel arrangement that includes a separate bit engine that corresponds to each level of the MLC LDPC signal that is operable to;
receive the estimate of the logarithm of the probability of the symbol of the MLC LDPC signal;
for each level of the MLC LDPC signal, the corresponding bit engine of the plurality of bit engines is operable to receive the updated plurality of edge messages with respect to the plurality of check nodes; and
for each level of the MLC LDPC signal, the corresponding bit engine of the plurality of bit engines is operable to perform bit node processing that involves updating a plurality of edge messages with respect to a plurality of bit nodes.
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Abstract
IPHD (Iterative Parallel Hybrid Decoding) of various MLC (Multi-Level Code) signals. Various embodiments are provided by which IPHD may be performed on MLC LDPC (Multi-Level Code Low Density Parity Check) coded modulation signals mapped using a plurality of mappings. This IPHD may also be performed on MLC LDPC coded modulation signals mapped using only a singe mapping as well. In addition, various embodiments are provided by which IPHD may be performed on ML TC (Multi-Level Turbo Code) signals. These principles of IPHD, shown with respect to various embodiments IPHD of MLC LDPC coded modulation signals as well as the IPHD of ML TC signals, may be extended to performing IPHD of other signal types as well. Generally speaking, based on the degree of the MLC signal, a corresponding number of parallel paths operate in cooperation to decode the various levels of the MLC signal.
64 Citations
34 Claims
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1. A decoder that is operable to perform IPHD (Iterative Parallel Hybrid Decoding) on a MLC (Multi-Level Code) LDPC (Low Density Parity Check) signal, the decoder comprising:
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an initialize edge message functional block that is operable to;
receive I, Q (In-phase, Quadrature) values corresponding to a symbol of the MLC LDPC signal; and
initialize a plurality of edge messages with respect to a plurality of bit nodes to a plurality of predetermined values for each level of the MLC LDPC signal;
a plurality of check engines in a parallel arrangement that includes a separate check engine that corresponds to each level of the MLC LDPC signal that is operable to;
for each level of the MLC LDPC signal, the corresponding check engine of the plurality of check engines is operable to receive the initialized plurality of edge messages with respect to a plurality of bit nodes from the initialize edge message functional block; and
for each level of the MLC LDPC signal, the corresponding check engine of the plurality of check engines is operable to perform check node processing that involves updating a plurality of edge messages with respect to a plurality of check nodes;
a symbol update engine that is operable to;
for each level of the MLC LDPC signal, receive the updated plurality of edge messages with respect to the plurality of check nodes from the plurality of check engines;
receive the I, Q values corresponding to the symbol of the MLC LDPC signal;
calculate a plurality of symbol metrics using the I, Q values;
calculate a plurality of LLR (Log-Likelihood Ratio) bit metrics using the plurality of symbol metrics;
calculate a plurality of logarithms of probabilities of bits of the symbol of the MLC LDPC signal using the plurality of LLR bit metrics and the updated pluralities of edge messages with respect to the plurality of check nodes corresponding to all levels of the MLC LDPC signal; and
estimate a logarithm of a probability of the symbol of the MLC LDPC signal using the plurality of logarithms of probabilities of bits of the symbol of the MLC LDPC signal using and at least one symbol metric of the plurality of symbol metrics; and
a plurality of bit engines in a parallel arrangement that includes a separate bit engine that corresponds to each level of the MLC LDPC signal that is operable to;
receive the estimate of the logarithm of the probability of the symbol of the MLC LDPC signal;
for each level of the MLC LDPC signal, the corresponding bit engine of the plurality of bit engines is operable to receive the updated plurality of edge messages with respect to the plurality of check nodes; and
for each level of the MLC LDPC signal, the corresponding bit engine of the plurality of bit engines is operable to perform bit node processing that involves updating a plurality of edge messages with respect to a plurality of bit nodes. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A decoder that is operable to perform IPHD (Iterative Parallel Hybrid Decoding) on a MLC (Multi-Level Code) LDPC (Low Density Parity Check) signal, the decoder comprising:
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an initialize edge message functional block that is operable to;
receive I, Q (In-phase, Quadrature) values corresponding to a symbol of the MLC LDPC signal; and
initialize a plurality of edge messages with respect to a plurality of bit nodes to a plurality of predetermined values;
a plurality of check engines in a parallel arrangement that includes a separate check engine that corresponds to each level of the MLC LDPC signal that is operable to;
for each level of the MLC LDPC signal, the corresponding check engine of the plurality of check engines is operable to receive the initialized plurality of edge messages with respect to a plurality of bit nodes from the initialize edge message functional block; and
for each level of the MLC LDPC signal, the corresponding check engine of the plurality of check engines is operable to perform check node processing that involves updating a plurality of edge messages with respect to a plurality of check nodes; and
a plurality of bit engines in a parallel arrangement that includes a separate bit engine that corresponds to each level of the MLC LDPC signal that is operable to;
for each level of the MLC LDPC signal, the corresponding bit engine of the plurality of bit engines is operable to receive I, Q values corresponding to the symbol of the MLC LDPC signal;
for each level of the MLC LDPC signal, the corresponding bit engine of the plurality of bit engines is operable to receive the updated pluralities of edge messages with respect to the plurality of check nodes corresponding to all levels of the MLC LDPC signal; and
for each level of the MLC LDPC signal, the corresponding bit engine of the plurality of bit engines is operable to perform bit node processing that involves updating a plurality of edge messages with respect to a plurality of bit nodes. - View Dependent Claims (14, 15, 16, 17, 18)
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19. A decoder that is operable to perform IPHD (Iterative Parallel Hybrid Decoding) on a ML TC (Multi-Level Turbo Code) signal, the decoder comprising:
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a first plurality of metric update functional blocks in a parallel arrangement that includes a separate metric update functional block that corresponds to each level of the ML TC signal such that for each level of the ML TC signal, the corresponding metric update functional block of the first plurality of metric update functional blocks is operable to;
receive I, Q (In-phase, Quadrature) values corresponding to a symbol of the ML TC signal;
calculate a first plurality of symbol metrics using the I, Q values; and
calculate a first plurality of LLR (Log-Likelihood Ratio) bit metrics using the first plurality of symbol metrics;
a first plurality of SISOs (Soft-In Soft-Out decoders) in a parallel arrangement that includes a separate SISO that corresponds to each level of the ML TC signal such that for each level of the ML TC signal, the corresponding SISO of the first plurality of SISOs is operable to;
receive the first plurality of LLR bit metrics; and
calculate first extrinsic information that corresponds to at least one information bit that has been encoded within the symbol of the ML TC signal using the first plurality of LLR bit metrics;
a plurality of interleavers in a parallel arrangement that includes a separate interleaver that corresponds to each level of the ML TC signal such that for each level of the ML TC signal, the corresponding interleaver of the plurality of interleavers is operable to;
receive the first extrinsic information; and
interleave the first extrinsic information to generate first APP (a priori probability) information;
a second plurality of metric update functional blocks in a parallel arrangement that includes a separate metric update functional block that corresponds to each level of the ML TC signal such that for each level of the ML TC signal, the corresponding metric update functional block of the second plurality of metric update functional blocks is operable to;
receive I, Q values corresponding to the symbol of the ML TC signal;
calculate a second plurality of symbol metrics using the I, Q values;
calculate a second plurality of LLR bit metrics using the second plurality of symbol metrics;
receive the first APP informations corresponding to all levels of the ML TC signal; and
update the second plurality of LLR bit metrics using the second plurality of LLR bit metrics and the first APP information; and
a second plurality of SISOs in a parallel arrangement that includes a separate SISO that corresponds to each level of the ML TC signal such that for each level of the ML TC signal, the corresponding SISO of the second plurality of SISOs is operable to;
receive the updated plurality of LLR bit metrics;
calculate second extrinsic information that corresponds to the at least one information bit that has been encoded within the symbol of the ML TC signal using the updated second plurality of LLR bit metrics;
a plurality of de-interleavers in a parallel arrangement that includes a separate de-interleaver that corresponds to each level of the ML TC signal such that for each level of the ML TC signal, the corresponding de-interleaver of the plurality of de-interleavers is operable to;
receive the second extrinsic information; and
interleave the second extrinsic information to generate second APP information. - View Dependent Claims (20, 21, 22)
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23. A method for performing IPHD (Iterative Parallel Hybrid Decoding) on a MLC (Multi-Level Code) LDPC (Low Density Parity Check) signal, the method comprising:
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receiving I, Q (In-phase, Quadrature) values corresponding to a symbol of the MLC LDPC signal;
initializing a plurality of edge messages with respect to a plurality of bit nodes to a plurality of predetermined values for each level of the MLC LDPC signal;
for each level of the MLC LDPC signal, receiving the initialized plurality of edge messages with respect to a plurality of bit nodes from the initialize edge message functional block;
for each level of the MLC LDPC signal, performing check node processing that involves updating a plurality of edge messages with respect to a plurality of check nodes;
for each level of the MLC LDPC signal, receiving the updated plurality of edge messages with respect to the plurality of check nodes;
calculating a plurality of symbol metrics using the I, Q values;
calculating a plurality of LLR (Log-Likelihood Ratio) bit metrics using the plurality of symbol metrics;
calculating a plurality of logarithms of probabilities of bits of the symbol of the MLC LDPC signal using the plurality of LLR bit metrics and the updated pluralities of edge messages with respect to the plurality of check nodes corresponding to all levels of the MLC LDPC signal;
estimating a logarithm of a probability of the symbol of the MLC LDPC signal using the plurality of logarithms of probabilities of bits of the symbol of the MLC LDPC signal using and at least one symbol metric of the plurality of symbol metrics;
receiving the estimate of the logarithm of the probability of the symbol of the MLC LDPC signal;
for each level of the MLC LDPC signal, receiving the updated plurality of edge messages with respect to the plurality of check nodes; and
for each level of the MLC LDPC signal, performing bit node processing that involves updating a plurality of edge messages with respect to a plurality of bit nodes. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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Specification