Apparatus and method for phase lock loop gain control using unit current sources

• US 20050168297A1
• Filed: 03/31/2005
• Published: 08/04/2005
• Est. Priority Date: 03/20/2001
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Ramon A. Gomez
• Inventors: Gomez, Ramon A.
• Granted Patent: US 7,355,485 B2
• Time in Patent Office: Days
• US Class Current: 331/175
• CPC Class Codes: H03B 2200/0046 including measures to switch the gain of an amplifier
• CPC Class Codes: H03B 2200/0048 including measures to switch the frequency band, e.g. by harmonic selection
• CPC Class Codes: H03B 2200/005 including measures to switch a capacitor
• CPC Class Codes: H03B 2201/02 Varying the frequency of the oscillations by electronic means
• CPC Class Codes: H03B 2201/0208 the means being an element with a variable capacitance, e.g. capacitance diode
• CPC Class Codes: H03B 2201/025 the means being an electronic switch for switching in or out oscillator elements
• CPC Class Codes: H03B 5/1212 the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
• CPC Class Codes: H03B 5/1215 the current source or degeneration circuit being in common to both transistors of the pair, e.g. a cross-coupled long-tailed pair
• CPC Class Codes: H03B 5/1228 the amplifier comprising one or more field effect transistors
• CPC Class Codes: H03B 5/1243 the means comprising voltage variable capacitance diodes
• CPC Class Codes: H03B 5/1253 the transistors being field-effect transistors
• CPC Class Codes: H03B 5/1265 switched capacitors
• CPC Class Codes: H03B 5/1278 the parameter being an amplitude of a signal, e.g. maintaining a constant output amplitude over the frequency range
• CPC Class Codes: H03D 7/165 at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature combined with amplitude demodulation H03D1/2245, combined with angle demodulation H03D3/007; N-path filters H03H19/002
• CPC Class Codes: H03D 7/18 Modifications of frequency-changers for eliminating image frequencies H03D7/16 takes precedence
• CPC Class Codes: H03J 2200/10 Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 5/244 using electronic means
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/099 : concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/1072 : by changing characteristics of the charge pump, e.g. changing the gain
• CPC Class Codes: H03L 7/18 : using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL. The reference scale current is generated based on a PLL control that specifics certain PLL characteristics such as reference frequency, loop bandwidth, and loop damping. Therefore, the reference pump current can be efficiently optimized for changing PLL operating conditions, in addition to compensating for variable VCO gain.

Claims

1-35. -35. (canceled)

36. A method of compensating the gain of a phase lock loop (PLL), comprising:

receiving a first control signal that is representative of an output frequency of said PLL;

receiving a second control signal that is representative of a characteristic of said PLL; and

generating a charge pump current for said PLL based on said first control signal and said second control signal.

37. The method of claim 36, wherein said characteristic of said PLL comprises one of a reference frequency, a loop bandwidth, and a damping factor of said PLL.

38. The method of claim 36, wherein said generating comprises:

selecting a charge pump current value from a plurality of charge pump current values based on said first control signal and said second control signal, and

converting said selected charge pump current value from a digital value to analog.

39. The method of claim 38, wherein said plurality of charge pump current values correspond to different combinations of characteristics of said PLL.

40. The method of claim 38, wherein said plurality of charge pump current values correspond to different output frequencies of said PLL.

41. The method of claim 38, wherein said plurality of charge pump current values comprise multiple sets of charge pump current values, each set of charge pump current values corresponding to a different output frequency of said PLL.

42. The method of claim 41, wherein individual charge pump current values in said set of charge pump current values correspond to different combination of characteristics of said PLL, but have a common output frequency of said PLL.

43. The method of claim 38, wherein said PLL comprises a voltage controlled oscillator (VCO) comprising a number of capacitors forming a resonant circuit for said VCO, and said first control signal represents a capacitor switched into said resonant circuit of said VCO.

44. The method of claim 43, wherein each of said plurality of charge pump current values is determined so as to compensate for variable VCO gain that occurs when a corresponding capacitor of said number of capacitors is switched into said VCO.

45. A circuit that generates a charge pump current in a phase lock loop (PLL), comprising:

means for storing a plurality of charge pump current values, each charge pump current value based on a PLL characteristic comprising at least one of a reference frequency, a loop bandwidth, and a damping factor of said PLL; and

means for converting a charge pump current value selected from said plurality of charge pump current values to an analog reference pump current for said charge pump.

46. The circuit of claim 45, wherein each of said charge pump current values is determined to compensate for variations in at least one of said PLL characteristics.

47. The circuit of claim 45, wherein said phase lock loop comprises a voltage controlled oscillator (VCO) comprising resonant circuit, each charge pump current value based on a capacitance switched into said resonant circuit of said VCO.

48. The circuit of claim 47, wherein each charge pump current value is determined to compensate for variable VCO gain that occurs when said corresponding capacitance is switched into said resonant circuit of said VCO.

49. A method of generating an analog reference pump current for a charge pump in a phase lock loop (PLL) comprising a voltage controlled oscillator (VCO) with a resonant circuit, comprising:

receiving a PLL control signal representative of characteristics of said PLL comprising at least one of a reference frequency, a loop bandwidth, and a damping factor of said PLL;

selecting a charge pump current value from a plurality of charge pump current values stored in a memory device based said PLL control signal; and

converting said selected charge pump current value to an analog reference pump current for said charge pump.

50. The method of claim 49, wherein said selecting comprises selecting a charge pump current value that compensates for variations in at least one of said PLL characteristics.