Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction

• US 20050170591A1
• Filed: 04/01/2005
• Published: 08/04/2005
• Est. Priority Date: 06/26/2003
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: RJ Mears LLC (Atomera Incorporated)
• Inventors: Mears, Robert J., Stephenson, Robert John
• Granted Patent: US 7,045,377 B2
• Time in Patent Office: Days
• US Class Current: 438/289
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/152 with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method for making a semiconductor device may include forming a superlattice comprising a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. The method may further include forming a semiconductor layer adjacent the superlattice and comprising at least one first region therein including a first conductivity type dopant. At least one second region may be formed in the superlattice including a second conductivity type dopant to define, with the at least one first region, at least one semiconductor junction.

Claims

1. A method for making a semiconductor device comprising:

forming a superlattice comprising a plurality of stacked groups of layers;

each group of layers of the superlattice comprising a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying layer thereon;

the energy band-modifying layer comprising at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions;

forming a semiconductor layer adjacent the superlattice and comprising at least one first region therein including a first conductivity type dopant; and

forming at least one second region in the superlattice including a second conductivity type dopant to define, with the at least one first region, at least one semiconductor junction.

2. The method of claim 1 wherein the at least one first region and the at least one second region are in direct contact with one another.

3. The method of claim 1 wherein the at least one first region and the at least one second region are spaced from one another.

4. The method of claim 1 wherein the at least one first region and the at least one second region are arranged in a vertical direction so that the at least one semiconductor junction extends in a lateral direction.

5. The method of claim 1 wherein the at least one first region and the at least one second region are arranged in a lateral direction so that the at least one semiconductor junction extends in a vertical direction.

6. The method of claim 1 wherein each energy band-modifying layer comprises oxygen.

7. The method of claim 1 wherein each energy band-modifying layer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

8. The method of claim 1 wherein each energy band-modifying layer is a single monolayer thick.

9. The method of claim 1 wherein each base silicon portion is less than eight monolayers thick.

10. The method of claim 1 wherein forming the superlattice further comprises forming a base semiconductor cap layer on an uppermost group of layers.

11. The method of claim 1 wherein all of the base silicon portions are a same number of monolayers thick.

12. The method of claim 1 wherein at least some of the base silicon portions are a different number of monolayers thick.

13. A method for making a semiconductor device comprising:

forming a superlattice comprising a plurality of stacked groups of layers;

each group of layers of the superlattice comprising a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying layer thereon;

the energy band-modifying layer comprising at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions;

forming a semiconductor layer adjacent the superlattice and comprising at least one first region therein including a first conductivity type dopant; and

forming at least one second region in the superlattice including a second conductivity type dopant to define, with the at least one first region, at least one semiconductor junction, the at least one first region and the at least one second region being in direct contact with one another.

14. The method of claim 13 wherein the at least one first region and the at least one second region are arranged in a vertical direction so that the at least one semiconductor junction extends in a lateral direction.

15. The method of claim 13 wherein the at least one first region and the at least one second region are arranged in a lateral direction so that the at least one semiconductor junction extends in a vertical direction.

16. The method of claim 13 wherein each energy band-modifying layer is a single monolayer thick.

17. The method of claim 13 wherein each base silicon portion is less than eight monolayers thick.

18. The method of claim 13 wherein forming the superlattice further comprises forming a base semiconductor cap layer on an uppermost group of layers.

19. The method of claim 13 wherein all of the base silicon portions are a same number of monolayers thick.

20. The method of claim 13 wherein at least some of the base silicon portions are a different number of monolayers thick.