Novel multi-state memory

• US 20050180211A1
• Filed: 04/14/2005
• Published: 08/18/2005
• Est. Priority Date: 08/07/1997
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Daniel C. Guterman, Yupin Kawing Fong
• Inventors: Fong, Yupin Kawing, Guterman, Daniel C.
• Granted Patent: US 7,345,934 B2
• Time in Patent Office: Days
• US Class Current: 365/185.30
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.

Claims

1-41. -41. (canceled)

42. A storage device comprising:

a semiconductor memory for storing data, the memory including a plurality of units of data access;

means for reading the data from each unit of data access of the memory;

error detection and correction means for detecting and correcting an error of the read data for each unit of data access; and

means for rewriting data in an area in which error correction is carried out, back in the same read area when an error is detected in the read data.

43. The storage device of claim 42, wherein said unit of data access is a sector.

44. A storage device comprising:

a semiconductor memory for storing data, the memory including a plurality of units of data access;

means for reading the data from each unit of data access of the memory;

error detection and correction means for detecting and correcting an error of the read data for each unit of data access;

means for recording an error count about the read data for each unit of data access; and

means for carrying out a comparison of a value of the error count with a predetermined value when an error is detected in the read data, and for rewriting data in an area in which error correction of the data is carried out in the same area on the basis of a result of the comparison.

45. The storage device of claim 44, wherein said unit of data access is a sector.

46. A storage device comprising:

a semiconductor memory for storing data, the memory including a plurality of units of data access;

means for reading the data from each unit of data access of the memory;

error detection and correction means for detecting and correcting an error of the read data for each unit of data access;

means for recording an error count about the read data for each unit of data access; and

means for carrying out a comparison of a value of the error count with a predetermined value when an error is detected in the read data, and for rewriting data in an area in which error correction is carried out, in one of the same area and another area on the basis of a result of the comparison.

47. The storage device of claim 46, wherein said unit of data access is a sector.

48. A storage device comprising:

a semiconductor memory for storing data, the memory including a plurality of units of data access;

read circuitry connectable to the memory, whereby for each of said units of data access the data quality is determined simultaneously with the data content; and

error correction circuitry connectable to the memory, whereby an error of the read data content can be corrected on the basis of said data quality, comprising programming circuitry connectable to the memory for writing data in an area in which a read process is carried out in a location on the basis of said data quality.

49. The storage device of claim 48, wherein said error correction circuitry further comprises:

a counter for each unit of data access incrementing a count when an error correction process is performed on the area in which a read process is carried;

a comparator to compare a of a value of the count with a predetermined value when an error correction process is performed on the area in which a read process is carried, wherein said location is determined on the basis of said comparison.

50. The storage device of claim 49, wherein in response to said count being less than the predetermined value, data is written in the area in which the read process is carried out.

51. The storage device of claim 49, wherein in response to said count being equal to the predetermined value, the data is rewritten in an area different from that in which the read process is carried out and the value of the count is reset.

52. The storage device of claim 48, wherein said unit of data access is a sector.

53. The storage device of claim 48, wherein units of data access comprises multi-state memory cells.

54. The storage device of claim 53, wherein in response to said data quality, the error correction circuitry performs additional programming on an under-programmed cell.

55. The storage device of claim 53, wherein said error correction circuitry further comprises:

erase circuitry, wherein in response to said data quality, the error correction circuitry erases and rewrites said area in which a read process is carried out.

56-71. -71. (canceled)

72. A storage apparatus to be coupled with a system bus for receiving a write request accompanied with a data through said system bus from a host system comprising:

a nonvolatile flash semiconductor memory which includes a plurality of memory blocks and a management area, and

a controller unit which is coupled with said system bus and said nonvolatile flash semiconductor memory and which carries out error detection and correction operations with respect to read data from, one block of said plurality of memory blocks of said nonvolatile flash semiconductor memory,

wherein said controller unit carries out a recording operation of a count of said error detection and correction operations into said management area within said nonvolatile flash semiconductor memory.

73. A storage apparatus according to claim 72,

wherein data after said error detection and correction operations is stored in the same block of plurality of memory blocks when an error is detected and corrected in the read block of said plurality of memory blocks within said nonvolatile flash semiconductor memory in a read operation.

74. A storage apparatus according to claim 72,

wherein data after said error detection and correction operations is stored in the different block of plurality of memory blocks when an error is detected and corrected in the read block of said plurality of memory blocks within said nonvolatile flash semiconductor memory in a read operation and when said count of said error detection and correction operations within said read block of plurality of memory blocks exceeds a predetermined level.