Methods for fabricating fuse programmable three dimensional integrated circuits

• US 20050181546A1
• Filed: 04/11/2005
• Published: 08/18/2005
• Est. Priority Date: 07/08/2002
• Status: Active Grant

• Current Assignee: Liberty Patents LLC
• Original Assignee: Tier Logic, Inc.
• Inventors: Madurawe, Raminda Udaya
• Granted Patent: US 7,312,109 B2
• Time in Patent Office: Days
• US Class Current: 438/132
• CPC Class Codes: H01L 21/822 the substrate being a semiconductor, using silicon technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 23/5258 the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]

Abstract

A method of fabricating a field programmable integrated circuit comprised of: constructing a semiconductor device comprising a fuse circuit to customize the logic content of a programmable logic circuit; and attaching said semiconductor device in a detachable lid package, wherein the fuses are customized in the field by detaching the lid and blowing one or more fuse elements. The said method further comprised of: providing a custom hard-wire pattern in lieu of the fuse circuit, wherein the programmable logic circuit timing is identical between the fuse circuit and hard-wire options.

Claims

1. A method of fabricating a field programmable integrated circuit comprised of:

constructing a semiconductor device comprising a fuse circuit to customize the logic content of a programmable logic circuit; and

attaching said semiconductor device in a detachable lid package, wherein the fuses are customized in the field by detaching the lid and blowing one or more fuse elements.

2. The method of claim 1, further comprised of:

providing a custom hard-wire pattern in lieu of the fuse circuit, wherein the programmable logic circuit timing is identical between the fuse circuit and hard-wire options.

3. The method of claim 1, further comprised of:

fabricating digital circuits and said programmable logic circuit on a semiconductor substrate; and

fabricating interconnect and routing layers above the digital circuits and the programmable logic circuit; and

fabricating said fuse circuit above the interconnect and routing layers.

4. The method of claim 1, further comprised of:

coupling each programmable node in the programmable logic circuit to two fuse elements; and

coupling one of said fuse elements to a logic one rail, and coupling the other of said fuse elements to a logic zero rail, wherein customizing the fuse circuit comprises blowing one or the other of said fuse elements.

5. The method of claim 4, wherein the fuse elements are programmed by one of thermal, electrical, optical, mechanical, magnetic, chemical and vibrational means.

6. The method of claim 4, wherein the fuse elements are programmed by an optical laser beam.

7. The method of claim 4, wherein the fabrication process sequence further comprises:

forming NMOS and PMOS transistors on a semiconductor substrate;

depositing above the NMOS and PMOS transistors an interconnect and routing structure comprising one or more metallization modules, each said module further comprised of;

depositing and polishing an inter metal dielectric layer;

forming inter metal contact plugs; and

depositing metal and forming metal tracks;

depositing an isolation dielectric material and performing CMP to isolate the interconnect and routing structure;

forming contact plugs to contact the top metal layer in the interconnect structure;

depositing one or more metal layers comprising a fuse metal layer with desired characteristics for rapid and reliable fuse blow;

depositing an isolation dielectric material; and

applying a pad mask and etching pads.

8. A method of forming a programmable semiconductor device comprised of:

fabricating digital circuits comprising a programmable logic circuit on a substrate;

fabricating an interconnect and routing structure substantially above the digital circuits; and

fabricating a programmable fuse circuit above the routing structure to program said programmable logic circuit, wherein the fuse circuit is programmed to store binary data values.

9. The method of claim 8, further comprised of:

coupling each programmable node in the programmable logic circuit to two fuse elements; and

coupling one of said fuse elements to a logic one rail, and coupling the other of said fuse elements to a logic zero rail;

wherein, programming the fuse circuit comprises blowing one or the other of said fuse elements.

10. The method of claim 8, wherein the fuse elements are blown by one of thermal, electrical, optical, mechanical, magnetic, chemical and vibrational means.

11. The method of claim 8, wherein the fuse elements are blown by an optical laser beam.

12. The method of claim 8, wherein the digital circuits and interconnect and routing structure fabrication utilizes a logic process sequence.

13. The method of claim 12, wherein the logic process sequence further comprises:

forming a P-type substrate;

creating a twin well;

developing a shallow trench isolation;

performing a sacrificial oxide;

generating a PMOS Vt mask and implant;

generating a NMOS Vt mask and implant;

developing gate oxidation;

depositing gate poly (GP);

applying the GP mask and etch;

applying an LDN mask and implant;

applying an LDP mask and implant;

depositing a spacer oxide and etching the spacer oxide;

depositing Nickel;

performing RTA anneal—

Ni salicidation (S/D/G regions &

interconnect)

etching to remove unreacted Nickel;

depositing ILD oxide and performing CMP;

applying a C1 mask and etch;

forming a W plug and performing CMP;

depositing M1;

applying a M1 mask &

etch; and

performing back end metallization.

14. The method of claim 8, wherein the programmable fuse fabrication process sequence further comprises:

depositing an isolation dielectric material and performing CMP to isolate the interconnect and routing structure;

forming contact plugs to contact the top metal layer in the interconnect structure to the fuse elements;

depositing one or more metal layers comprising a fuse metal layer with desired characteristics for rapid and reliable fuse blow;

depositing an isolation dielectric material above the fuse metal; and

applying a pad mask and etching pads.

15. The method of claim 8, wherein a given fuse blow pattern in the fuse circuit has a corresponding mask configurable conductive pattern in lieu of said fuse circuit, both of which identically program said programmable logic circuit.

16. The method of claim 15, wherein one or more of the digital circuit characteristics comprises a timing characteristic substantially unchanged by the programmable option.

17. The method of claim 8, further comprised of using a bit stream of digital logic one and logic zero generated by a computer aided design automation tool during the place and route phase of custom logic placement and timing optimization to generate the fuse blow pattern.

18. A method of fabricating a programmable integrated circuit comprised of:

fabricating a packaged semiconductor device comprising only a laser fuse circuit as the top most metal layer to customize the logic content of a programmable logic circuit.

19. The method of claim 18, wherein each programmable node in the logic circuit is coupled to two laser fuse elements, one fuse element coupled to a power bus and the other fuse element coupled to a ground bus.

20. The method of claim 18, wherein the package comprises a detachable lid to remove the lid in the field and blow the fuse elements with an optical laser beam.