Apparatus and method for controlling instructions at time of failure of branch prediction

  • US 20050188187A1
  • Filed: 04/26/2005
  • Published: 08/25/2005
  • Est. Priority Date: 05/28/2003
  • Status: Active Grant
First Claim
Patent Images

1. An apparatus for controlling instructions, comprising:

  • an instruction fetch control unit configured to exercise such control as to fetch instructions from a memory unit storing the instructions therein that are to be executed according to an out-of-order method;

    an instruction buffer configured to store temporarily the instructions supplied from the memory unit;

    an instruction decoder configured to decode the instructions supplied from the instruction buffer;

    a branch instruction prediction unit configured to make branch prediction with respect to an instruction; and

    a branch prediction control unit configured to control the instruction fetch control unit, the instruction buffer, the instruction decoder, and the branch instruction prediction unit, wherein when the branch prediction control unit ascertains that the branch prediction by the branch instruction prediction unit is erroneous, the branch prediction control unit outputs to the instruction fetch control unit a signal for suppressing an instruction fetch request already supplied to the memory unit and outputs to the instruction buffer a signal for nullifying the instruction buffer during a period between a point in time at which the ascertainment is made by the branch prediction control unit that the branch prediction by the branch instruction prediction unit is erroneous and a point in time at which the instruction buffer fetches a correct instruction from the memory unit.

View all claims
    ×
    ×

    Thank you for your feedback

    ×
    ×