Method for forming a trench MOSFET having self-aligned features

• US 20050191794A1
• Filed: 04/20/2005
• Published: 09/01/2005
• Est. Priority Date: 05/20/2003
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Becky Losee, Dean Probst, Robert Herrick
• Inventors: Probst, Dean, Herrick, Robert, Losee, Becky
• Granted Patent: US 7,344,943 B2
• Time in patent office: Days
• US Class Current: 438/135
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: Y10S 257/905 Plural dram cells share common contact or common trench

Abstract

A semiconductor device is formed as follows. A plurality of trenches is formed in a silicon layer. An insulating layer filling an upper portion of each trench is formed. Exposed silicon is removed from adjacent the trenches to expose an edge of the insulating layer in each trench, such that the exposed edge of the insulating layer in each trench defines a portion of each contact opening formed between every two adjacent trenches.

Claims

1. A method of forming a semiconductor device, comprising:

forming a plurality of trenches in a silicon layer;

forming an insulating layer filling an upper portion of each trench; and

removing exposed silicon from adjacent the trenches to expose an edge of the insulating layer in each trench, the exposed edge of the insulating layer in each trench defining a portion of each contact opening formed between every two adjacent trenches.

2. The method of claim 1 further comprising:

prior to removing exposed silicon, forming a first region of a first conductivity type in the silicon layer so that after said exposed silicon removing step, of the first region, only a portion adjacent each trench sidewall remains, the remaining portion of the first region adjacent each trench sidewall forming a source region of the semiconductor device,

wherein the step of removing exposed silicon further exposes a sidewall of each source region such that the exposed edge of the insulating layer in each trench together with the exposed sidewall of a corresponding source region form one sidewall of a contact opening between every two adjacent trenches.

3. The method of claim 1 further comprising:

forming a gate electrode filling a lower portion of each trench, the insulating layer substantially filling a remaining portion of each trench.

4. A method of forming a semiconductor device, comprising:

forming a plurality of trenches in a silicon layer;

forming a first region along a surface of the silicon layer;

forming an insulating layer fully contained within each trench, the insulating layer in each trench extending directly over a portion of the first region adjacent each trench sidewall; and

removing exposed silicon from adjacent each trench until, of the first region, only the portions adjacent the trench sidewalls remain, the remaining portions of the first region adjacent the trench sidewalls forming source regions which are self-aligned to the trenches.