States encoding in multi-bit flash cells

• US 20050201401A1
• Filed: 01/18/2005
• Published: 09/15/2005
• Est. Priority Date: 03/14/2004
• Status: Active Grant

• Current Assignee: Western Digital Israel Limited (Western Digital Corporation)
• Original Assignee: M-Systems Flash Disk Pioneers Ltd. (Western Digital Corporation)
• Inventors: Lasser, Menahem
• Granted Patent: US 7,310,347 B2
• Time in Patent Office: Days
• US Class Current: 370/412
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

N data bits are stored in ┌N/M┐ cells by programming each cell with up to M of the bits according to a valid, nonserial bit ordering that satisfies one of the following criteria: Either the number of threshold voltage comparisons needed to read all M bits sequentially is at most 1 more than the smallest such number, or the largest number of threshold voltage comparisons needed to read any bit is minimized, or the smallest number of threshold voltage comparisons needed to read any bit is minimized, or the difference between the largest and smallest number of threshold voltage comparisons needed to read any bit statically is at most 1 more than the smallest such difference, or the difference between the largest and smallest number of threshold voltage comparisons needed to read any bit dynamically is minimized.

Claims

1. A method of storing N bits of data, comprising the steps of:

(a) providing ┌

N/M┐

cells; and

(b) programming each cell with up to M of the bits according to a valid, nonserial bit ordering that satisfies a criterion selected from the group consisting of;

(i) a number of threshold voltage comparisons for sequentially and statically reading said M bits exceeds a minimum said number of threshold voltage comparisons by at most 1,

(ii) a maximum number of threshold voltage comparisons for statically reading any one of said M bits is minimized,

(iii) a minimum number of threshold voltage comparisons for statically reading any one of said M bits is minimized,

(iv) a maximum number of threshold voltage comparisons for statically reading any one of said M bits exceeds a minimum number of threshold voltage comparisons for statically reading any one of said M bits by at most 1,

(v) a number of threshold voltage comparisons for sequentially and dynamically reading said M bits exceeds a minimum said number of threshold voltage comparisons by at most 1,

(vi) a maximum number of threshold voltage comparisons for dynamically reading any one of said M bits is minimized,

(vii) a minimum number of threshold voltage comparisons for dynamically reading any one of said M bits is minimized, and

(viii) a maximum number of threshold voltage comparisons for dynamically reading any one of said M bits exceeds a minimum number of threshold voltage comparisons for dynamically reading any one of said M bits by at most 1;

wherein M is at least 3.

2. The method of claim 1, wherein said criterion is that said number of threshold voltage comparisons for sequentially and statically reading said M bits exceeds said minimum number of threshold voltage comparisons by at most 1

3. The method of claim 2, wherein M=3, and wherein said number of threshold voltage comparisons for sequentially and statically reading said M bits is 7.

4. The method of claim 2, wherein M=4, and wherein said number of threshold voltage comparisons for sequentially and statically reading said M bits is 15.

5. The method of claim 2, wherein said number of threshold voltage comparisons for sequentially and statically reading said M bits is equal to said minimum number of threshold voltage comparisons.

6. The method of claim 5, wherein M=3 and wherein said bit ordering is one of:

{7, 6, 4, 5, 1, 0, 2, 3} and

{7, 6, 4, 5, 1, 3, 2, 0}.

7. The method of claim 5, wherein M=4 and wherein said bit ordering is one of:

{15, 14, 12, 13, 9, 8, 10, 11, 3, 2, 0, 4, 6, 7, 5, 1},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 2, 0, 1, 5, 4, 6, 7},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 2, 0, 1, 5, 7, 6, 4},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 2, 6, 4, 0, 1, 5, 7},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 2, 6, 7, 5, 4, 0, 1},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 2, 6, 7, 5, 1, 0, 4},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 1, 0, 4, 5, 7, 6, 2},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 1, 0, 2, 6, 4, 5, 7},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 1, 0, 2, 6, 7, 5, 4},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 1, 5, 4, 0, 2, 6, 7},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 1, 5, 7, 6, 4, 0, 2},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 1, 5, 7, 6, 2, 0, 4},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 7, 6, 4, 5, 1, 0, 2},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 7, 6, 2, 0, 4, 5, 1},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 7, 6, 2, 0, 1, 5, 4},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 7, 5, 4, 6, 2, 0, 1},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 7, 5, 1, 0, 4, 6, 2},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 7, 5, 1, 0, 2, 6, 4},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 4, 6, 2, 3, 1, 5, 7},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 4, 6, 2, 3, 7, 5, 1},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 4, 6, 7, 5, 1, 3, 2},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 4, 5, 1, 3, 2, 6, 7},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 4, 5, 1, 3, 7, 6, 2},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 4, 5, 7, 6, 2, 3, 1},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 2, 6, 4, 5, 1, 3, 7},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 2, 6, 4, 5, 7, 3, 1},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 2, 6, 7, 3, 1, 5, 4},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 2, 3, 1, 5, 4, 6, 7},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 2, 3, 1, 5, 7, 6, 4},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 2, 3, 7, 6, 4, 5, 1},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 1, 5, 4, 6, 2, 3, 7},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 1, 5, 4, 6, 7, 3, 2},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 1, 5, 7, 3, 2, 6, 4},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 1, 3, 2, 6, 4, 5, 7},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 1, 3, 2, 6, 7, 5, 4} and

{15, 14, 12, 13, 9, 11, 10, 8, 0, 1, 3, 7, 5, 4, 6, 2}.

8. The method of claim 2, wherein said number of threshold voltage comparisons for sequentially and statically reading said M bits exceeds said minimum number of threshold voltage comparisons by 1.

9. The method of claim 8, wherein M=3, and wherein said number of threshold voltage comparisons for sequentially and statically reading said M bits is 8.

10. The method of claim 8, wherein M=3 and wherein said bit ordering is one of:

{7, 6, 2, 3, 5, 4, 0, 1},

{7, 6, 4, 0, 2, 3, 5, 1},

{7, 6, 4, 0, 5, 1, 3, 2},

{7, 6, 4, 5, 0, 2, 3, 1},

{7, 6, 4, 5, 0, 1, 3, 2},

{7, 6, 4, 5, 1, 0, 3, 2},

{7, 6, 4, 5, 1, 3, 0, 2},

{7, 6, 4, 5, 3, 2, 0, 1},

{7, 6, 4, 5, 3, 1, 0, 2},

{7, 6, 5, 4, 0, 2, 3, 1},

{7, 6, 5, 4, 0, 1, 3, 2},

{7, 5, 6, 4, 0, 2, 3, 1},

{7, 5, 6, 4, 0, 1, 3, 2},

{7, 5, 1, 3, 6, 4, 0, 2} and

{7, 3, 6, 4, 5, 1, 0, 2}.

11. The method of claim 1, wherein said criterion is that said maximum number of threshold voltage comparisons for statically reading any one of said M bits is minimized.

12. The method of claim 11, wherein M=3, and wherein said maximum number of threshold voltage comparisons for statically reading any one of said M bits is 3.

13. The method of claim 11, wherein M=4, and wherein said maximum number of threshold voltage comparisons for statically reading any one of said M bits is 5.

14. The method of claim 11, wherein M=3 and wherein said bit ordering is one of:

{7, 6, 2, 4, 5, 1, 3, 0},

{7, 6, 2, 4, 5, 3, 1, 0},

{7, 6, 4, 2, 3, 5, 1, 0},

{7, 6, 4, 0, 2, 3, 5, 1},

{7, 6, 4, 0, 5, 1, 3, 2},

{7, 6, 4, 5, 1, 3, 2, 0},

{7, 6, 5, 1, 3, 2, 4, 0},

{7, 5, 6, 2, 3, 1, 4, 0},

{7, 3, 6, 4, 5, 1, 2, 0} and

{7, 3, 6, 4, 5, 1, 0, 2}.

15. The method of claim 11, wherein M=4 and wherein said bit ordering is one of:

{15, 14, 12, 13, 9, 8, 10, 11, 3, 1, 5, 7, 6, 2, 0, 4},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 7, 5, 1, 0, 4, 6, 2},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 7, 5, 1, 0, 2, 6, 4},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 4, 6, 2, 3, 7, 5, 1},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 4, 5, 1, 3, 7, 6, 2}

{15, 14, 12, 13, 9, 11, 10, 8, 0, 2, 6, 7, 3, 1, 5, 4} and

{15, 14, 12, 13, 9, 11, 10, 8, 0, 1, 5, 7, 3, 2, 6, 4}.

16. The method of claim 1, wherein said criterion is that said minimum number of threshold voltage comparisons for statically reading any one of said M bits is minimized.

17. The method of claim 16, wherein M=3, and wherein said minimum number of threshold voltage comparisons for statically reading any one of said M bits is 1.

18. The method of claim 16, wherein M=4, and wherein said minimum number of threshold voltage comparisons for statically reading any one of said M bits is 1.

19. The method of claim 16, wherein M=3 and wherein said bit ordering is one of:

{7, 6, 2, 3, 4, 0, 5, 1},

{7, 6, 2, 3, 4, 5, 0, 1},

{7, 6, 2, 3, 4, 5, 1, 0},

{7, 6, 2, 3, 5, 4, 0, 1},

{7, 6, 2, 3, 5, 4, 1, 0},

{7, 6, 2, 3, 5, 1, 4, 0},

{7, 6, 4, 5, 2, 0, 1, 3},

{7, 6, 4, 5, 2, 0, 3, 1},

{7, 6, 4, 5, 2, 1, 0, 3},

{7, 6, 4, 5, 2, 1, 3, 0},

{7, 6, 4, 5, 2, 3, 0, 1},

{7, 6, 4, 5, 2, 3, 1, 0},

{7, 6, 4, 5, 0, 2, 1, 3},

{7, 6, 4, 5, 0, 2, 3, 1},

{7, 6, 4, 5, 0, 1, 2, 3},

{7, 6, 4, 5, 0, 1, 3, 2},

{7, 6, 4, 5, 0, 3, 1, 2},

{7, 6, 4, 5, 0, 3, 2, 1},

{7, 6, 4, 5, 1, 2, 0, 3},

{7, 6, 4, 5, 1, 2, 3, 0},

{7, 6, 4, 5, 1, 0, 2, 3},

{7, 6, 4, 5, 1, 0, 3, 2},

{7, 6, 4, 5, 1, 3, 2, 0},

{7, 6, 4, 5, 1, 3, 0, 2},

{7, 6, 4, 5, 3, 2, 0, 1},

{7, 6, 4, 5, 3, 2, 1, 0},

{7, 6, 4, 5, 3, 0, 2, 1},

{7, 6, 4, 5, 3, 0, 1, 2},

{7, 6, 4, 5, 3, 1, 2, 0},

{7, 6, 4, 5, 3, 1, 0, 2},

{7, 6, 5, 4, 2, 0, 1, 3},

{7, 6, 5, 4, 2, 0, 3, 1},

{7, 6, 5, 4, 2, 1, 0, 3},

{7, 6, 5, 4, 2, 1, 3, 0},

{7, 6, 5, 4, 2, 3, 0, 1},

{7, 6, 5, 4, 2, 3, 1, 0},

{7, 6, 5, 4, 0, 2, 1, 3},

{7, 6, 5, 4, 0, 2, 3, 1},

{7, 6, 5, 4, 0, 1, 2, 3},

{7, 6, 5, 4, 0, 1, 3, 2},

{7, 6, 5, 4, 0, 3, 1, 2},

{7, 6, 5, 4, 0, 3, 2, 1},

{7, 6, 5, 4, 1, 2, 0, 3},

{7, 6, 5, 4, 1, 2, 3, 0},

{7, 6, 5, 4, 1, 0, 2, 3},

{7, 6, 5, 4, 1, 0, 3, 2},

{7, 6, 5, 4, 1, 3, 2, 0},

{7, 6, 5, 4, 1, 3, 0, 2},

{7, 6, 5, 4, 3, 2, 0, 1},

{7, 6, 5, 4, 3, 0, 2, 1},

{7, 6, 5, 4, 3, 0, 1, 2},

{7, 6, 5, 4, 3, 1, 2, 0},

{7, 6, 5, 4, 3, 1, 0, 2},

{7, 6, 3, 2, 4, 0, 5, 1},

{7, 6, 3, 2, 4, 5, 0, 1},

{7, 6, 3, 2, 4, 5, 1, 0},

{7, 6, 3, 2, 5, 4, 0, 1},

{7, 6, 3, 2, 5, 4, 1, 0},

{7, 6, 3, 2, 5, 1, 4, 0},

{7, 5, 6, 4, 2, 0, 1, 3},

{7, 5, 6, 4, 2, 0, 3, 1},

{7, 5, 6, 4, 2, 1, 0, 3},

{7, 5, 6, 4, 2, 1, 3, 0},

{7, 5, 6, 4, 2, 3, 0, 1},

{7, 5, 6, 4, 2, 3, 1, 0},

{7, 5, 6, 4, 0, 2, 1, 3},

{7, 5, 6, 4, 0, 2, 3, 1},

{7, 5, 6, 4, 0, 1, 2, 3},

{7, 5, 6, 4, 0, 1, 3, 2},

{7, 5, 6, 4, 0, 3, 1, 2},

{7, 5, 6, 4, 0, 3, 2, 1},

{7, 5, 6, 4, 1, 2, 0, 3},

{7, 5, 6, 4, 1, 2, 3, 0},

{7, 5, 6, 4, 1, 0, 2, 3},

{7, 5, 6, 4, 1, 0, 3, 2},

{7, 5, 6, 4, 1, 3, 2, 0},

{7, 5, 6, 4, 1, 3, 0, 2},

{7, 5, 6, 4, 3, 2, 0, 1},

{7, 5, 6, 4, 3, 2, 1, 0},

{7, 5, 6, 4, 3, 0, 2, 1},

{7, 5, 6, 4, 3, 0, 1, 2},

{7, 5, 6, 4, 3, 1, 2, 0},

{7, 5, 6, 4, 3, 1, 0, 2},

{7, 5, 1, 3, 6, 2, 4, 0},

{7, 5, 1, 3, 6, 4, 2, 0},

{7, 5, 1, 3, 6, 4, 0, 2},

{7, 5, 3, 1, 6, 2, 4, 0},

{7, 5, 3, 1, 6, 4, 2, 0},

{7, 5, 3, 1, 6, 4, 0, 2},

{7, 3, 6, 2, 4, 0, 5, 1},

{7, 3, 6, 2, 4, 5, 0, 1},

{7, 3, 6, 2, 4, 5, 1, 0},

{7, 3, 6, 2, 5, 4, 0, 1},

{7, 3, 6, 2, 5, 4, 1, 0},

{7, 3, 6, 2, 5, 1, 4, 0},

{7, 3, 5, 1, 6, 2, 4, 0},

{7, 3, 5, 1, 6, 4, 2, 0} and

{7, 3, 5, 1, 6, 4, 0, 2}.

20. The method of claim 16, wherein M=4 and wherein said bit ordering is one of:

{15, 14, 12, 13, 9, 8, 10, 11, 3, 2, 0, 4, 6, 7, 5, 1},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 2, 0, 1, 5, 4, 6, 7},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 2, 0, 1, 5, 7, 6, 4},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 2, 6, 4, 0, 1, 5, 7},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 2, 6, 7, 5, 4, 0, 1},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 2, 6, 7, 5, 1, 0, 4},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 1, 0, 4, 5, 7, 6, 2},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 1, 0, 2, 6, 4, 5, 7},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 1, 0, 2, 6, 7, 5, 4},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 1, 5, 4, 0, 2, 6, 7},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 1, 5, 7, 6, 4, 0, 2},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 1, 5, 7, 6, 2, 0, 4},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 7, 6, 4, 5, 1, 0, 2},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 7, 6, 2, 0, 4, 5, 1},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 7, 6, 2, 0, 1, 5, 4},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 7, 5, 4, 6, 2, 0, 1},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 7, 5, 1, 0, 4, 6, 2},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 7, 5, 1, 0, 2, 6, 4},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 4, 6, 2, 3, 1, 5, 7},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 4, 6, 2, 3, 7, 5, 1},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 4, 6, 7, 5, 1, 3, 2},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 4, 5, 1, 3, 2, 6, 7},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 4, 5, 1, 3, 7, 6, 2},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 4, 5, 7, 6, 2, 3, 1},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 2, 6, 4, 5, 1, 3, 7},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 2, 6, 4, 5, 7, 3, 1},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 2, 6, 7, 3, 1, 5, 4},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 2, 3, 1, 5, 4, 6, 7},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 2, 3, 1, 5, 7, 6, 4},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 2, 3, 7, 6, 4, 5, 1},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 1, 5, 4, 6, 2, 3, 7},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 1, 5, 4, 6, 7, 3, 2},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 1, 5, 7, 3, 2, 6, 4},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 1, 3, 2, 6, 4, 5, 7},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 1, 3, 2, 6, 7, 5, 4} and

{15, 14, 12, 13, 9, 11, 10, 8, 0, 1, 3, 7, 5, 4, 6, 2}.

21. The method of claim 1, wherein said criterion is that said maximum number of threshold voltage comparisons for statically reading any one of said M bits exceeds said minimum number of threshold voltage comparisons for statically reading any one of said M bits by at most 1.

22. The method of claim 21, wherein said maximum number of threshold voltage comparisons for statically reading any one of said M bits equals said minimum number of threshold voltage comparisons for statically reading any one of said M bits.

23. The method of claim 22, wherein M=3, and wherein 3 said threshold voltage comparisons are needed to statically read any one of said M bits.

24. The method of claim 22, wherein M=3 and wherein said bit ordering is one of:

{7, 6, 2, 4, 5, 1, 3, 0},

{7, 6, 2, 4, 5, 3, 1, 0},

{7, 6, 4, 2, 3, 5, 1, 0} and

{7, 6, 5, 1, 3, 2, 4, 0}.

25. The method of claim 21, wherein said maximum number of threshold voltage comparisons for statically reading any one of said M bits exceeds said minimum number of threshold voltage comparisons for statically reading any one of said M bits by 1.

26. The method of claim 25, wherein M=3, wherein said maximum number of threshold voltage comparisons for statically reading any one of said M bits is 4, and wherein said minimum number of threshold voltage comparisons for statically reading any one of said M bits is 3.

27. The method of claim 25, wherein M=4, wherein said maximum number of threshold voltage comparisons for statically reading any one of said M bits is 5, and wherein said minimum number of threshold voltage comparisons for statically reading any one of said M bits is 4.

28. The method of claim 25, wherein M=3 and wherein said bit ordering is one of:

{7, 6, 2, 4, 5, 0, 3, 1},

{7, 6, 2, 4, 5, 3, 0, 1},

{7, 6, 2, 5, 4, 0, 3, 1},

{7, 6, 4, 2, 5, 0, 1, 3},

{7, 6, 4, 2, 5, 1, 0, 3},

{7, 6, 4, 2, 3, 0, 5, 1},

{7, 6, 4, 2, 3, 5, 0, 1},

{7, 6, 4, 0, 2, 3, 5, 1},

{7, 6, 4, 0, 5, 2, 1, 3},

{7, 6, 4, 0, 5, 2, 3, 1},

{7, 6, 4, 0, 5, 1, 3, 2},

{7, 6, 4, 0, 5, 3, 1, 2},

{7, 6, 4, 0, 5, 3, 2, 1},

{7, 6, 4, 0, 3, 2, 5, 1},

{7, 6, 4, 0, 3, 5, 1, 2},

{7, 6, 4, 3, 2, 0, 5, 1},

{7, 6, 4, 3, 5, 1, 0, 2},

{7, 6, 5, 2, 4, 0, 1, 3},

{7, 6, 5, 1, 2, 4, 0, 3},

{7, 6, 5, 1, 4, 2, 0, 3},

{7, 6, 5, 1, 3, 4, 0, 2},

{7, 6, 5, 3, 2, 4, 0, 1},

{7, 6, 5, 3, 1, 4, 0, 2},

{7, 6, 3, 5, 4, 2, 0, 1},

{7, 6, 3, 5, 4, 0, 2, 1},

{7, 5, 6, 2, 4, 1, 0, 3},

{7, 5, 6, 2, 1, 4, 0, 3},

{7, 5, 6, 2, 3, 4, 0, 1},

{7, 5, 6, 1, 4, 0, 2, 3},

{7, 5, 6, 3, 2, 4, 0, 1},

{7, 5, 6, 3, 1, 4, 0, 2},

{7, 5, 1, 6, 4, 0, 3, 2},

{7, 5, 3, 6, 4, 0, 1, 2},

{7, 5, 3, 6, 4, 1, 0, 2},

{7, 3, 6, 4, 5, 2, 0, 1},

{7, 3, 6, 4, 5, 0, 2, 1},

{7, 3, 6, 5, 4, 2, 0, 1},

{7, 3, 6, 5, 4, 0, 2, 1},

{7, 3, 5, 6, 4, 0, 1, 2} and

{7, 3, 5, 6, 4, 1, 0, 2}.

29. The method of claim 25, wherein M=4 and wherein said bit ordering is one of:

{15, 14, 12, 8, 0, 10, 11, 3, 2, 6, 4, 13, 9, 1, 5, 7},

{15, 14, 12, 13, 9, 8, 0, 4, 6, 10, 2, 11, 3, 1, 5, 7},

{15, 14, 12, 13, 9, 8, 0, 10, 2, 6, 4, 5, 1, 11, 3, 7},

{15, 14, 12, 13, 9, 1, 5, 4, 6, 10, 8, 0, 2, 11, 3, 7},

{15, 14, 12, 13, 9, 11, 3, 10, 2, 6, 4, 8, 0, 1, 5, 7},

{15, 14, 12, 13, 9, 11, 3, 1, 5, 4, 8, 0, 10, 2, 6, 7},

{15, 14, 12, 13, 5, 9, 8, 10, 2, 6, 4, 0, 1, 11, 3, 7},

{15, 14, 12, 13, 5, 9, 1, 11, 10, 8, 0, 4, 6, 2, 3, 7},

{15, 14, 12, 13, 5, 9, 11, 10, 2, 6, 4, 8, 0, 1, 3, 7},

{15, 14, 10, 2, 6, 12, 13, 9, 11, 3, 1, 8, 0, 4, 5, 7},

{15, 14, 6, 12, 8, 0, 4, 13, 9, 11, 10, 2, 3, 1, 5, 7},

{15, 14, 6, 12, 8, 10, 11, 3, 2, 0, 4, 13, 9, 1, 5, 7},

{15, 14, 6, 12, 13, 9, 8, 10, 2, 0, 4, 5, 1, 11, 3, 7} and

{15, 14, 6, 12, 13, 9, 11, 10, 2, 8, 0, 4, 5, 1, 3, 7}.

30. The method of claim 1, wherein said criterion is that said number of threshold voltage comparisons for sequentially and dynamically reading said M bits exceeds said minimum number of threshold voltage comparisons by at most 1.

31. The method of claim 30, wherein said number of threshold voltage comparisons for sequentially and dynamically reading said M bits is equal to said minimum number of threshold voltage comparisons.

32. The method of claim 31, wherein M=3, and wherein said number of threshold voltage comparisons for sequentially and dynamically reading said M bits is 5.

33. The method of claim 31, wherein M=4, and wherein said number of threshold voltage comparisons for sequentially and dynamically reading said M bits is 9.

34. The method of claim 31, wherein M=3 and wherein said bit ordering is {7, 6, 4, 5, 1, 3, 2, 0}.

35. The method of claim 31, wherein M=4 and wherein said bit ordering is one of:

{15, 14, 12, 13, 9, 8, 10, 11, 3, 2, 0, 4, 6, 7, 5, 1},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 2, 0, 1, 5, 7, 6, 4},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 2, 6, 7, 5, 4, 0, 1},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 2, 6, 7, 5, 1, 0, 4},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 1, 0, 4, 5, 7, 6, 2},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 1, 0, 2, 6, 4, 5, 7},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 1, 0, 2, 6, 7, 5, 4},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 1, 5, 7, 6, 4, 0, 2},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 7, 6, 4, 5, 1, 0, 2},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 7, 6, 2, 0, 4, 5, 1},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 7, 6, 2, 0, 1, 5, 4},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 7, 5, 4, 6, 2, 0, 1},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 4, 6, 7, 5, 1, 3, 2},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 4, 5, 7, 6, 2, 3, 1},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 2, 6, 4, 5, 7, 3, 1},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 2, 3, 1, 5, 4, 6, 7},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 2, 3, 1, 5, 7, 6, 4},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 2, 3, 7, 6, 4, 5, 1},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 1, 5, 4, 6, 7, 3, 2},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 1, 3, 2, 6, 4, 5, 7},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 1, 3, 2, 6, 7, 5, 4} and

{15, 14, 12, 13, 9, 11, 10, 8, 0, 1, 3, 7, 5, 4, 6, 2}.

36. The method of claim 30, wherein said number of threshold voltage comparisons for sequentially and dynamically reading said M bits exceeds said minimum number of threshold voltage comparisons by 1.

37. The method of claim 36, wherein M=3, and wherein said number of threshold voltage comparisons for sequentially and dynamically reading said M bits is 6.

38. The method of claim 36, wherein M=3 and wherein said bit orderings is one of:

{7, 6, 2, 4, 5, 1, 3, 0},

{7, 6, 2, 4, 5, 3, 1, 0},

{7, 6, 2, 3, 4, 5, 0, 1},

{7, 6, 2, 3, 4, 5, 1, 0},

{7, 6, 2, 3, 5, 4, 0, 1},

{7, 6, 2, 3, 5, 4, 1, 0},

{7, 6, 2, 3, 5, 1, 4, 0},

{7, 6, 4, 2, 3, 5, 1, 0},

{7, 6, 4, 0, 2, 3, 5, 1},

{7, 6, 4, 0, 5, 1, 3, 2},

{7, 6, 4, 5, 2, 3, 0, 1},

{7, 6, 4, 5, 2, 3, 1, 0},

{7, 6, 4, 5, 0, 2, 3, 1},

{7, 6, 4, 5, 0, 1, 2, 3},

{7, 6, 4, 5, 0, 1, 3, 2},

{7, 6, 4, 5, 0, 3, 2, 1},

{7, 6, 4, 5, 1, 2, 3, 0},

{7, 6, 4, 5, 1, 0, 2, 3},

{7, 6, 4, 5, 1, 0, 3, 2},

{7, 6, 4, 5, 1, 3, 0, 2},

{7, 6, 4, 5, 3, 2, 0, 1},

{7, 6, 4, 5, 3, 2, 1, 0},

{7, 6, 4, 5, 3, 1, 2, 0},

{7, 6, 4, 5, 3, 1, 0, 2},

{7, 6, 5, 4, 2, 3, 0, 1},

{7, 6, 5, 4, 2, 3, 1, 0},

{7, 6, 5, 4, 0, 2, 3, 1},

{7, 6, 5, 4, 0, 1, 2, 3},

{7, 6, 5, 4, 0, 1, 3, 2},

{7, 6, 5, 4, 0, 3, 2, 1},

{7, 6, 5, 4, 1, 2, 3, 0},

{7, 6, 5, 4, 1, 0, 2, 3},

{7, 6, 5, 4, 1, 0, 3, 2},

{7, 6, 5, 4, 1, 3, 2, 0},

{7, 6, 5, 4, 3, 2, 0, 1},

{7, 6, 5, 1, 3, 2, 4, 0},

{7, 6, 3, 2, 4, 5, 0, 1},

{7, 6, 3, 2, 4, 5, 1, 0},

{7, 6, 3, 2, 5, 4, 0, 1},

{7, 6, 3, 2, 5, 4, 1, 0},

{7, 5, 6, 2, 3, 1, 4, 0},

{7, 5, 6, 4, 2, 0, 1, 3},

{7, 5, 6, 4, 2, 0, 3, 1},

{7, 5, 6, 4, 2, 1, 3, 0},

{7, 5, 6, 4, 2, 3, 1, 0},

{7, 5, 6, 4, 0, 2, 1, 3},

{7, 5, 6, 4, 0, 2, 3, 1},

{7, 5, 6, 4, 0, 1, 3, 2},

{7, 5, 6, 4, 0, 3, 1, 2},

{7, 5, 6, 4, 1, 3, 2, 0},

{7, 5, 6, 4, 1, 3, 0, 2},

{7, 5, 6, 4, 3, 1, 2, 0},

{7, 5, 6, 4, 3, 1, 0, 2},

{7, 5, 1, 3, 6, 2, 4, 0},

{7, 5, 1, 3, 6, 4, 2, 0},

{7, 5, 1, 3, 6, 4, 0, 2},

{7, 5, 3, 1, 6, 4, 2, 0},

{7, 5, 3, 1, 6, 4, 0, 2},

{7, 3, 6, 2, 4, 0, 5, 1},

{7, 3, 6, 2, 4, 5, 1, 0},

{7, 3, 6, 2, 5, 1, 4, 0},

{7, 3, 6, 4, 5, 1, 2, 0},

{7, 3, 6, 4, 5, 1, 0, 2} and

{7, 3, 5, 1, 6, 2, 4, 0}.

39. The method of claim 1, wherein said criterion is that said maximum number of threshold voltage comparisons for dynamically reading any one of said M bits is minimized.

40. The method of claim 39, wherein M=3, and wherein said maximum number of threshold voltage comparisons for dynamically reading any one of said M bits is 2.

41. The method of claim 39, wherein M=4, and wherein said maximum number of threshold voltage comparisons for dynamically reading any one of said M bits is 3.

42. The method of claim 39, wherein M=3 and wherein said bit ordering is one of:

{7, 6, 2, 4, 5, 1, 3, 0},

{7, 6, 2, 4, 5, 3, 1, 0},

{7, 6, 4, 2, 3, 5, 1, 0},

{7, 6, 4, 0, 2, 3, 5, 1},

{7, 6, 4, 0, 5, 1, 3, 2},

{7, 6, 4, 5, 1, 3, 2, 0},

{7, 6, 5, 1, 3, 2, 4, 0},

{7, 5, 6, 2, 3, 1, 4, 0},

{7, 3, 6, 4, 5, 1, 2, 0} and

{7, 3, 6, 4, 5, 1, 0, 2}.

43. The method of claim 39, wherein M=4 and wherein said bit ordering is one of:

{15, 14, 12, 13, 9, 8, 10, 11, 3, 2, 0, 4, 6, 7, 5, 1},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 2, 0, 1, 5, 7, 6, 4},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 2, 6, 4, 0, 1, 5, 7},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 2, 6, 7, 5, 1, 0, 4},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 1, 0, 4, 5, 7, 6, 2},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 1, 0, 2, 6, 4, 5, 7},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 1, 0, 2, 6, 7, 5, 4},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 1, 5, 4, 0, 2, 6, 7},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 1, 5, 7, 6, 4, 0, 2},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 1, 5, 7, 6, 2, 0, 4},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 7, 6, 4, 5, 1, 0, 2},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 7, 6, 2, 0, 4, 5, 1},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 7, 6, 2, 0, 1, 5, 4},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 7, 5, 4, 6, 2, 0, 1},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 7, 5, 1, 0, 4, 6, 2},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 7, 5, 1, 0, 2, 6, 4},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 4, 6, 2, 3, 1, 5, 7},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 4, 6, 2, 3, 7, 5, 1},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 4, 6, 7, 5, 1, 3, 2},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 4, 5, 1, 3, 2, 6, 7},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 4, 5, 1, 3, 7, 6, 2},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 4, 5, 7, 6, 2, 3, 1},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 2, 6, 4, 5, 1, 3, 7},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 2, 6, 4, 5, 7, 3, 1},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 2, 6, 7, 3, 1, 5, 4},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 2, 3, 1, 5, 4, 6, 7},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 2, 3, 1, 5, 7, 6, 4},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 2, 3, 7, 6, 4, 5, 1},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 1, 5, 4, 6, 2, 3, 7},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 1, 5, 4, 6, 7, 3, 2},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 1, 5, 7, 3, 2, 6, 4},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 1, 3, 2, 6, 4, 5, 7},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 1, 3, 2, 6, 7, 5, 4} and

{15, 14, 12, 13, 9, 11, 10, 8, 0, 1, 3, 7, 5, 4, 6, 2}.

44. The method of claim 1, wherein said criterion is that said minimum number of threshold voltage comparisons for dynamically reading any one of said M bits is minimized.

45. The method of claim 44, wherein M=3, and wherein said minimum number of threshold voltage comparisons for dynamically reading any one of said M bits is 1.

46. The method of claim 44, wherein M=4, and wherein said minimum number of threshold voltage comparisons for dynamically reading any one of said M bits is 1.

47. The method of claim 44, wherein M=3 and wherein said bit ordering is one of:

{7, 6, 2, 3, 4, 0, 5, 1},

{7, 6, 2, 3, 4, 5, 0, 1},

{7, 6, 2, 3, 4, 5, 1, 0},

{7, 6, 2, 3, 5, 4, 0, 1},

{7, 6, 2, 3, 5, 4, 1, 0},

{7, 6, 2, 3, 5, 1, 4, 0},

{7, 6, 4, 5, 2, 0, 1, 3},

{7, 6, 4, 5, 2, 0, 3, 1},

{7, 6, 4, 5, 2, 1, 0, 3},

{7, 6, 4, 5, 2, 1, 3, 0},

{7, 6, 4, 5, 2, 3, 0, 1},

{7, 6, 4, 5, 2, 3, 1, 0},

{7, 6, 4, 5, 0, 2, 1, 3},

{7, 6, 4, 5, 0, 2, 3, 1},

{7, 6, 4, 5, 0, 1, 2, 3},

{7, 6, 4, 5, 0, 1, 3, 2},

{7, 6, 4, 5, 0, 3, 1, 2},

{7, 6, 4, 5, 0, 3, 2, 1},

{7, 6, 4, 5, 1, 2, 0, 3},

{7, 6, 4, 5, 1, 2, 3, 0},

{7, 6, 4, 5, 1, 0, 2, 3},

{7, 6, 4, 5, 1, 0, 3, 2},

{7, 6, 4, 5, 1, 3, 2, 0},

{7, 6, 4, 5, 1, 3, 0, 2},

{7, 6, 4, 5, 3, 2, 0, 1},

{7, 6, 4, 5, 3, 2, 1, 0},

{7, 6, 4, 5, 3, 0, 2, 1},

{7, 6, 4, 5, 3, 0, 1, 2},

{7, 6, 4, 5, 3, 1, 2, 0},

{7, 6, 4, 5, 3, 1, 0, 2},

{7, 6, 5, 4, 2, 0, 1, 3},

{7, 6, 5, 4, 2, 0, 3, 1},

{7, 6, 5, 4, 2, 1, 0, 3},

{7, 6, 5, 4, 2, 1, 3, 0},

{7, 6, 5, 4, 2, 3, 0, 1},

{7, 6, 5, 4, 2, 3, 1, 0},

{7, 6, 5, 4, 0, 2, 1, 3},

{7, 6, 5, 4, 0, 2, 3, 1},

{7, 6, 5, 4, 0, 1, 2, 3},

{7, 6, 5, 4, 0, 1, 3, 2},

{7, 6, 5, 4, 0, 3, 1, 2},

{7, 6, 5, 4, 0, 3, 2, 1},

{7, 6, 5, 4, 1, 2, 0, 3},

{7, 6, 5, 4, 1, 2, 3, 0},

{7, 6, 5, 4, 1, 0, 2, 3},

{7, 6, 5, 4, 1, 0, 3, 2},

{7, 6, 5, 4, 1, 3, 2, 0},

{7, 6, 5, 4, 1, 3, 0, 2},

{7, 6, 5, 4, 3, 2, 0, 1},

{7, 6, 5, 4, 3, 0, 2, 1},

{7, 6, 5, 4, 3, 0, 1, 2},

{7, 6, 5, 4, 3, 1, 2, 0},

{7, 6, 5, 4, 3, 1, 0, 2},

{7, 6, 3, 2, 4, 0, 5, 1},

{7, 6, 3, 2, 4, 5, 0, 1},

{7, 6, 3, 2, 4, 5, 1, 0},

{7, 6, 3, 2, 5, 4, 0, 1},

{7, 6, 3, 2, 5, 4, 1, 0},

{7, 6, 3, 2, 5, 1, 4, 0},

{7, 5, 6, 4, 2, 0, 1, 3},

{7, 5, 6, 4, 2, 0, 3, 1},

{7, 5, 6, 4, 2, 1, 0, 3},

{7, 5, 6, 4, 2, 1, 3, 0},

{7, 5, 6, 4, 2, 3, 0, 1},

{7, 5, 6, 4, 2, 3, 1, 0},

{7, 5, 6, 4, 0, 2, 1, 3},

{7, 5, 6, 4, 0, 2, 3, 1},

{7, 5, 6, 4, 0, 1, 2, 3},

{7, 5, 6, 4, 0, 1, 3, 2},

{7, 5, 6, 4, 0, 3, 1, 2},

{7, 5, 6, 4, 0, 3, 2, 1},

{7, 5, 6, 4, 1, 2, 0, 3},

{7, 5, 6, 4, 1, 2, 3, 0},

{7, 5, 6, 4, 1, 0, 2, 3},

{7, 5, 6, 4, 1, 0, 3, 2},

{7, 5, 6, 4, 1, 3, 2, 0},

{7, 5, 6, 4, 1, 3, 0, 2},

{7, 5, 6, 4, 3, 2, 0, 1},

{7, 5, 6, 4, 3, 2, 1, 0},

{7, 5, 6, 4, 3, 0, 2, 1},

{7, 5, 6, 4, 3, 0, 1, 2},

{7, 5, 6, 4, 3, 1, 2, 0},

{7, 5, 6, 4, 3, 1, 0, 2},

{7, 5, 1, 3, 6, 2, 4, 0},

{7, 5, 1, 3, 6, 4, 2, 0},

{7, 5, 1, 3, 6, 4, 0, 2},

{7, 5, 3, 1, 6, 2, 4, 0},

{7, 5, 3, 1, 6, 4, 2, 0},

{7, 5, 3, 1, 6, 4, 0, 2},

{7, 3, 6, 2, 4, 0, 5, 1},

{7, 3, 6, 2, 4, 5, 0, 1},

{7, 3, 6, 2, 4, 5, 1, 0},

{7, 3, 6, 2, 5, 4, 0, 1},

{7, 3, 6, 2, 5, 4, 1, 0},

{7, 3, 6, 2, 5, 1, 4, 0},

{7, 3, 5, 1, 6, 2, 4, 0},

{7, 3, 5, 1, 6, 4, 2, 0} and

{7, 3, 5, 1, 6, 4, 0, 2}.

48. The method of claim 44, wherein M=4 and wherein said bit ordering is one of:

{15, 14, 12, 13, 9, 8, 10, 11, 3, 2, 0, 4, 6, 7, 5, 1},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 2, 0, 1, 5, 4, 6, 7},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 2, 0, 1, 5, 7, 6, 4},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 2, 6, 4, 0, 1, 5, 7},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 2, 6, 7, 5, 4, 0, 1},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 2, 6, 7, 5, 1, 0, 4},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 1, 0, 4, 5, 7, 6, 2},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 1, 0, 2, 6, 4, 5, 7},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 1, 0, 2, 6, 7, 5, 4},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 1, 5, 4, 0, 2, 6, 7},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 1, 5, 7, 6, 4, 0, 2},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 1, 5, 7, 6, 2, 0, 4},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 7, 6, 4, 5, 1, 0, 2},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 7, 6, 2, 0, 4, 5, 1},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 7, 6, 2, 0, 1, 5, 4},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 7, 5, 4, 6, 2, 0, 1},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 7, 5, 1, 0, 4, 6, 2},

{15, 14, 12, 13, 9, 8, 10, 11, 3, 7, 5, 1, 0, 2, 6, 4},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 4, 6, 2, 3, 1, 5, 7},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 4, 6, 2, 3, 7, 5, 1},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 4, 6, 7, 5, 1, 3, 2},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 4, 5, 1, 3, 2, 6, 7},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 4, 5, 1, 3, 7, 6, 2},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 4, 5, 7, 6, 2, 3, 1},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 2, 6, 4, 5, 1, 3, 7},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 2, 6, 4, 5, 7, 3, 1},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 2, 6, 7, 3, 1, 5, 4},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 2, 3, 1, 5, 4, 6, 7},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 2, 3, 1, 5, 7, 6, 4},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 2, 3, 7, 6, 4, 5, 1},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 1, 5, 4, 6, 2, 3, 7},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 1, 5, 4, 6, 7, 3, 2},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 1, 5, 7, 3, 2, 6, 4},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 1, 3, 2, 6, 4, 5, 7},

{15, 14, 12, 13, 9, 11, 10, 8, 0, 1, 3, 2, 6, 7, 5, 4} and

{15, 14, 12, 13, 9, 11, 10, 8, 0, 1, 3, 7, 5, 4, 6, 2}.

49. The method of claim 1, wherein said criterion is that said maximum number of threshold voltage comparisons for dynamically reading any one of said M bits exceeds said minimum number of threshold voltages for dynamically reading any one of said M bits by at most 1.

50. The method of claim 49, wherein said maximum number of threshold voltage comparisons for dynamically reading any one of said M bits equals said minimum number of threshold voltage comparisons for dynamically reading any one of said M bits.

51. The method of claim 50, wherein M=3, and wherein 2 said threshold voltage comparisons are needed to dynamically read any one of said M bits.

52. The method of claim 50, wherein M=4 and wherein 3 said threshold voltage comparisons are needed to dynamically read any one of said M bits.

53. The method of claim 50, wherein M=3 wherein said bit ordering is one of:

{7, 6, 2, 4, 5, 1, 3, 0},

{7, 6, 2, 4, 5, 3, 1, 0},

{7, 6, 4, 2, 3, 5, 1, 0},

{7, 6, 4, 0, 2, 3, 5, 1},

{7, 6, 4, 0, 5, 1, 3, 2},

{7, 6, 5, 1, 3, 2, 4, 0},

{7, 5, 6, 2, 3, 1, 4, 0},

{7, 3, 6, 4, 5, 1, 2, 0},

{7, 3, 6, 4, 5, 1, 0, 2}.

54. The method of claim 50, wherein M=4 and wherein said bit ordering is one of:

{15, 14, 12, 8, 0, 10, 11, 3, 2, 6, 4, 13, 9, 1, 5, 7},

{15, 14, 12, 13, 9, 8, 0, 4, 6, 10, 2, 11, 3, 1, 5, 7},

{15, 14, 12, 13, 9, 8, 0, 10, 2, 6, 4, 5, 1, 11, 3, 7},

{15, 14, 12, 13, 9, 1, 5, 4, 6, 10, 8, 0, 2, 11, 3, 7},

{15, 14, 12, 13, 9, 11, 3, 10, 2, 6, 4, 8, 0, 1, 5, 7},

{15, 14, 12, 13, 9, 11, 3, 1, 5, 4, 8, 0, 10, 2, 6, 7},

{15, 14, 12, 13, 5, 9, 8, 10, 2, 6, 4, 0, 1, 11, 3, 7},

{15, 14, 12, 13, 5, 9, 1, 11, 10, 8, 0, 4, 6, 2, 3, 7},

{15, 14, 12, 13, 5, 9, 11, 10, 2, 6, 4, 8, 0, 1, 3, 7},

{15, 14, 10, 2, 6, 12, 13, 9, 11, 3, 1, 8, 0, 4, 5, 7},

{15, 14, 6, 12, 8, 0, 4, 13, 9, 11, 10, 2, 3, 1, 5, 7},

{15, 14, 6, 12, 8, 10, 11, 3, 2, 0, 4, 13, 9, 1, 5, 7},

{15, 14, 6, 12, 13, 9, 8, 10, 2, 0, 4, 5, 1, 11, 3, 7} and

{15, 14, 6, 12, 13, 9, 11, 10, 2, 8, 0, 4, 5, 1, 3, 7}.

55. The method of claim 49, wherein said maximum number of threshold voltage comparisons for dynamically reading any one of said M bits exceeds said minimum number of threshold voltage comparisons for dynamically reading any one of said M bits by 1.

56. The method of claim 55, wherein M=3, wherein said maximum number of threshold voltage comparisons for dynamically reading any one of said M bits is 3, and wherein said minimum number of threshold voltage comparisons for dynamically reading any one of said M bits is 2.

57. The method of claim 55, wherein M=4, wherein said maximum number of threshold voltage comparisons for dynamically reading any one of said M bits is 3, and wherein said minimum number of threshold voltage comparisons for dynamically reading any one of said M bits is 2.

58. The method of claim 55, wherein M=3 and wherein said bit ordering is one of:

{7, 6, 2, 4, 0, 5, 1, 3},

{7, 6, 2, 4, 0, 5, 3, 1},

{7, 6, 2, 4, 0, 3, 5, 1},

{7, 6, 2, 4, 5, 0, 1, 3},

{7, 6, 2, 4, 5, 0, 3, 1},

{7, 6, 2, 4, 5, 1, 0, 3},

{7, 6, 2, 4, 5, 3, 0, 1},

{7, 6, 2, 4, 3, 0, 5, 1},

{7, 6, 2, 4, 3, 5, 0, 1},

{7, 6, 2, 4, 3, 5, 1, 0},

{7, 6, 2, 5, 4, 0, 1, 3},

{7, 6, 2, 5, 4, 0, 3, 1},

{7, 6, 2, 5, 4, 1, 0, 3},

{7, 6, 2, 5, 4, 1, 3, 0},

{7, 6, 2, 5, 4, 3, 0, 1},

{7, 6, 2, 5, 4, 3, 1, 0},

{7, 6, 2, 5, 1, 4, 0, 3},

{7, 6, 2, 5, 1, 4, 3, 0},

{7, 6, 2, 5, 1, 3, 4, 0},

{7, 6, 2, 5, 3, 4, 0, 1},

{7, 6, 2, 5, 3, 4, 1, 0},

{7, 6, 2, 5, 3, 1, 4, 0},

{7, 6, 4, 2, 0, 5, 1, 3},

{7, 6, 4, 2, 0, 5, 3, 1},

{7, 6, 4, 2, 0, 3, 5, 1},

{7, 6, 4, 2, 5, 0, 1, 3},

{7, 6, 4, 2, 5, 0, 3, 1},

{7, 6, 4, 2, 5, 1, 0, 3},

{7, 6, 4, 2, 5, 1, 3, 0},

{7, 6, 4, 2, 5, 3, 0, 1},

{7, 6, 4, 2, 5, 3, 1, 0},

{7, 6, 4, 2, 3, 0, 5, 1},

{7, 6, 4, 2, 3, 5, 0, 1},

{7, 6, 4, 0, 2, 5, 1, 3},

{7, 6, 4, 0, 2, 5, 3, 1},

{7, 6, 4, 0, 5, 2, 1, 3},

{7, 6, 4, 0, 5, 2, 3, 1},

{7, 6, 4, 0, 5, 1, 2, 3},

{7, 6, 4, 0, 5, 3, 1, 2},

{7, 6, 4, 0, 5, 3, 2, 1},

{7, 6, 4, 0, 3, 2, 5, 1},

{7, 6, 4, 0, 3, 5, 1, 2},

{7, 6, 4, 0, 3, 5, 2, 1},

{7, 6, 4, 5, 1, 3, 2, 0},

{7, 6, 4, 3, 2, 0, 5, 1},

{7, 6, 4, 3, 2, 5, 0, 1},

{7, 6, 4, 3, 2, 5, 1, 0},

{7, 6, 4, 3, 0, 2, 5, 1},

{7, 6, 4, 3, 0, 5, 2, 1},

{7, 6, 4, 3, 0, 5, 1, 2},

{7, 6, 4, 3, 5, 2, 0, 1},

{7, 6, 4, 3, 5, 2, 1, 0},

{7, 6, 4, 3, 5, 0, 2, 1},

{7, 6, 4, 3, 5, 0, 1, 2},

{7, 6, 4, 3, 5, 1, 2, 0},

{7, 6, 4, 3, 5, 1, 0, 2},

{7, 6, 5, 2, 4, 0, 1, 3},

{7, 6, 5, 2, 4, 0, 3, 1},

{7, 6, 5, 2, 4, 1, 0, 3},

{7, 6, 5, 2, 4, 1, 3, 0},

{7, 6, 5, 2, 4, 3, 0, 1},

{7, 6, 5, 2, 4, 3, 1, 0},

{7, 6, 5, 2, 1, 4, 0, 3},

{7, 6, 5, 2, 1, 4, 3, 0},

{7, 6, 5, 2, 1, 3, 4, 0},

{7, 6, 5, 2, 3, 4, 0, 1},

{7, 6, 5, 2, 3, 4, 1, 0},

{7, 6, 5, 2, 3, 1, 4, 0},

{7, 6, 5, 1, 2, 4, 0, 3},

{7, 6, 5, 1, 2, 4, 3, 0},

{7, 6, 5, 1, 2, 3, 4, 0},

{7, 6, 5, 1, 4, 2, 0, 3},

{7, 6, 5, 1, 4, 2, 3, 0},

{7, 6, 5, 1, 4, 0, 2, 3},

{7, 6, 5, 1, 4, 0, 3, 2},

{7, 6, 5, 1, 4, 3, 2, 0},

{7, 6, 5, 1, 4, 3, 0, 2},

{7, 6, 5, 1, 3, 2, 4, 0},

{7, 6, 5, 1, 3, 4, 2, 0},

{7, 6, 5, 1, 3, 4, 0, 2},

{7, 6, 5, 3, 2, 4, 0, 1},

{7, 6, 5, 3, 2, 4, 1, 0},

{7, 6, 5, 3, 2, 1, 4, 0},

{7, 6, 5, 3, 4, 2, 0, 1},

{7, 6, 5, 3, 4, 2, 1, 0},

{7, 6, 5, 3, 4, 0, 2, 1},

{7, 6, 5, 3, 4, 0, 1, 2},

{7, 6, 5, 3, 4, 1, 2, 0},

{7, 6, 5, 3, 4, 1, 0, 2},

{7, 6, 5, 3, 1, 2, 4, 0},

{7, 6, 5, 3, 1, 4, 2, 0},

{7, 6, 5, 3, 1, 4, 0, 2},

{7, 6, 3, 4, 2, 0, 5, 1},

{7, 6, 3, 4, 2, 5, 0, 1},

{7, 6, 3, 4, 2, 5, 1, 0},

{7, 6, 3, 4, 0, 2, 5, 1},

{7, 6, 3, 4, 0, 5, 2, 1},

{7, 6, 3, 4, 0, 5, 1, 2},

{7, 6, 3, 4, 5, 2, 0, 1},

{7, 6, 3, 4, 5, 2, 1, 0},

{7, 6, 3, 4, 5, 0, 2, 1},

{7, 6, 3, 4, 5, 0, 1, 2},

{7, 6, 3, 4, 5, 1, 2, 0},

{7, 6, 3, 4, 5, 1, 0, 2},

{7, 6, 3, 5, 2, 4, 0, 1},

{7, 6, 3, 5, 2, 4, 1, 0},

{7, 6, 3, 5, 2, 1, 4, 0},

{7, 6, 3, 5, 4, 2, 0, 1},

{7, 6, 3, 5, 4, 2, 1, 0},

{7, 6, 3, 5, 4, 0, 2, 1},

{7, 6, 3, 5, 4, 0, 1, 2},

{7, 6, 3, 5, 4, 1, 2, 0},

{7, 6, 3, 5, 4, 1, 0, 2},

{7, 6, 3, 5, 1, 2, 4, 0},

{7, 6, 3, 5, 1, 4, 2, 0},

{7, 6, 3, 5, 1, 4, 0, 2},

{7, 5, 6, 2, 4, 0, 1, 3},

{7, 5, 6, 2, 4, 0, 3, 1},

{7, 5, 6, 2, 4, 1, 0, 3},

{7, 5, 6, 2, 4, 1, 3, 0},

{7, 5, 6, 2, 4, 3, 0, 1},

{7, 5, 6, 2, 4, 3, 1, 0},

{7, 5, 6, 2, 1, 4, 0, 3},

{7, 5, 6, 2, 1, 4, 3, 0},

{7, 5, 6, 2, 1, 3, 4, 0},

{7, 5, 6, 2, 3, 4, 0, 1},

{7, 5, 6, 2, 3, 4, 1, 0},

{7, 5, 6, 1, 2, 4, 0, 3},

{7, 5, 6, 1, 2, 4, 3, 0},

{7, 5, 6, 1, 2, 3, 4, 0},

{7, 5, 6, 1, 4, 2, 0, 3},

{7, 5, 6, 1, 4, 2, 3, 0},

{7, 5, 6, 1, 4, 0, 2, 3},

{7, 5, 6, 1, 4, 0, 3, 2},

{7, 5, 6, 1, 4, 3, 2, 0},

{7, 5, 6, 1, 4, 3, 0, 2},

{7, 5, 6, 1, 3, 2, 4, 0},

{7, 5, 6, 1, 3, 4, 2, 0},

{7, 5, 6, 1, 3, 4, 0, 2},

{7, 5, 6, 3, 2, 4, 0, 1},

{7, 5, 6, 3, 2, 4, 1, 0},

{7, 5, 6, 3, 2, 1, 4, 0},

{7, 5, 6, 3, 4, 2, 0, 1},

{7, 5, 6, 3, 4, 2, 1, 0},

{7, 5, 6, 3, 4, 0, 2, 1},

{7, 5, 6, 3, 4, 0, 1, 2},

{7, 5, 6, 3, 4, 1, 2, 0},

{7, 5, 6, 3, 4, 1, 0, 2},

{7, 5, 6, 3, 1, 2, 4, 0},

{7, 5, 6, 3, 1, 4, 2, 0},

{7, 5, 6, 3, 1, 4, 0, 2},

{7, 5, 1, 6, 2, 4, 0, 3},

{7, 5, 1, 6, 2, 4, 3, 0},

{7, 5, 1, 6, 2, 3, 4, 0},

{7, 5, 1, 6, 4, 2, 0, 3},

{7, 5, 1, 6, 4, 2, 3, 0},

{7, 5, 1, 6, 4, 0, 2, 3},

{7, 5, 1, 6, 4, 0, 3, 2},

{7, 5, 1, 6, 4, 3, 2, 0},

{7, 5, 1, 6, 4, 3, 0, 2},

{7, 5, 1, 6, 3, 2, 4, 0},

{7, 5, 1, 6, 3, 4, 2, 0},

{7, 5, 1, 6, 3, 4, 0, 2},

{7, 5, 3, 6, 2, 4, 0, 1},

{7, 5, 3, 6, 2, 4, 1, 0},

{7, 5, 3, 6, 2, 1, 4, 0},

{7, 5, 3, 6, 4, 2, 0, 1},

{7, 5, 3, 6, 4, 2, 1, 0},

{7, 5, 3, 6, 4, 0, 2, 1},

{7, 5, 3, 6, 4, 0, 1, 2},

{7, 5, 3, 6, 4, 1, 2, 0},

{7, 5, 3, 6, 4, 1, 0, 2},

{7, 5, 3, 6, 1, 2, 4, 0},

{7, 5, 3, 6, 1, 4, 2, 0},

{7, 5, 3, 6, 1, 4, 0, 2},

{7, 3, 6, 4, 2, 0, 5, 1},

{7, 3, 6, 4, 2, 5, 0, 1},

{7, 3, 6, 4, 2, 5, 1, 0},

{7, 3, 6, 4, 0, 2, 5, 1},

{7, 3, 6, 4, 0, 5, 2, 1},

{7, 3, 6, 4, 0, 5, 1, 2},

{7, 3, 6, 4, 5, 2, 0, 1},

{7, 3, 6, 4, 5, 2, 1, 0},

{7, 3, 6, 4, 5, 0, 2, 1},

{7, 3, 6, 4, 5, 0, 1, 2},

{7, 3, 6, 5, 2, 4, 0, 1},

{7, 3, 6, 5, 2, 4, 1, 0},

{7, 3, 6, 5, 2, 1, 4, 0},

{7, 3, 6, 5, 4, 2, 0, 1},

{7, 3, 6, 5, 4, 2, 1, 0},

{7, 3, 6, 5, 4, 0, 2, 1},

{7, 3, 6, 5, 4, 0, 1, 2},

{7, 3, 6, 5, 4, 1, 2, 0},

{7, 3, 6, 5, 4, 1, 0, 2},

{7, 3, 6, 5, 1, 2, 4, 0},

{7, 3, 6, 5, 1, 4, 2, 0},

{7, 3, 6, 5, 1, 4, 0, 2},

{7, 3, 5, 6, 2, 4, 0, 1},

{7, 3, 5, 6, 2, 4, 1, 0},

{7, 3, 5, 6, 2, 1, 4, 0},

{7, 3, 5, 6, 4, 2, 0, 1},

{7, 3, 5, 6, 4, 2, 1, 0},

{7, 3, 5, 6, 4, 0, 2, 1},

{7, 3, 5, 6, 4, 0, 1, 2},

{7, 3, 5, 6, 4, 1, 2, 0},

{7, 3, 5, 6, 4, 1, 0, 2},

{7, 3, 5, 6, 1, 2, 4, 0},

{7, 3, 5, 6, 1, 4, 2, 0} and

{7, 3, 5, 6, 1, 4, 0, 2}.

59. The method of claim 55, wherein M=4 and wherein said bit ordering is one of:

{15, 14, 12, 4, 13, 9, 8, 10, 11, 3, 2, 6, 7, 5, 1, 0},

{15, 14, 12, 13, 9, 8, 10, 2, 11, 3, 7, 6, 4, 5, 1, 0},

{15, 14, 12, 13, 9, 1, 8, 10, 11, 3, 2, 6, 7, 5, 4, 0},

{15, 14, 12, 13, 9, 11, 10, 2, 3, 7, 6, 4, 5, 1, 8, 0},

{15, 14, 12, 13, 9, 11, 3, 1, 5, 7, 6, 4, 8, 10, 2, 0},

{15, 14, 12, 13, 5, 4, 8, 9, 11, 10, 2, 6, 7, 3, 1, 0},

{15, 14, 6, 7, 13, 12, 8, 9, 11, 10, 2, 3, 1, 5, 4, 0},

{15, 13, 5, 7, 14, 12, 8, 10, 11, 9, 1, 3, 2, 6, 4, 0} and

{15, 7, 14, 12, 13, 9, 8, 10, 11, 3, 2, 6, 4, 5, 1, 0}.

60. A memory device comprising:

(a) a memory that includes K cells; and

(b) a controller operative to store N bits of data in said cells by programming each said cell with up to M=┌

N/K┐

of said bits according to a valid, nonserial bit ordering that satisfies a criterion selected from the group consisting of;

(i) a number of threshold voltage comparisons for sequentially and statically reading said M bits exceeds a minimum said number of threshold voltage comparisons by at most 1,

(ii) a maximum number of threshold voltage comparisons for statically reading any one of said M bits is minimized,

(iii) a minimum number of threshold voltage comparisons for statically reading any one of said M bits is minimized,

(iv) a maximum number of threshold voltage comparisons for statically reading any one of said M bits exceeds a minimum number of threshold voltage comparisons for statically reading any one of said M bits by at most 1,

(v) a number of threshold voltage comparisons for sequentially and dynamically reading said M bits exceeds a minimum said number of threshold voltage comparisons by at most 1,

(vi) a maximum number of threshold voltage comparisons for dynamically reading any one of said M bits is minimized,

(vii) a minimum number of threshold voltage comparisons for dynamically reading any one of said M bits is minimized, and

(viii) a maximum number of threshold voltage comparisons for dynamically reading any one of said M bits exceeds a minimum number of threshold voltage comparisons for dynamically reading any one of said M bits by at most 1;

wherein M is at least 3.

61. A method of storing N bits of data, comprising the steps of:

(a) providing ┐

N/M┐

cells; and

(b) programming each cell with up to M of the bits according to a valid, nonserial bit ordering that satisfies a criterion selected from the group consisting of;

(i) a total number of transitions in said bit ordering is a minimum said number of transitions,

(ii) said total number of transitions in said bit ordering exceeds a minimum said number of transitions by 1,

(iii) a maximum said number of transitions in said bit ordering is a minimum said maximum number of transitions,

(iv) a minimum said number of transitions in said bit ordering is a minimum said minimum number of transitions,

(v) said bit ordering is such that all M bits have a common number of transitions, and

(vi) said bit ordering is such that a number of transitions of any bit differs from a number of transitions of any other bit by at most 1;

wherein M is at least 3.

62. The method of claim 61, wherein said total number of transitions in said bit ordering is a minimum said number of transitions.

63. The method of claim 62, wherein M=3 and wherein said total number of transitions is 7.

64. The method of claim 62, wherein M=4 and wherein said total number of transitions is 15.

65. The method of claim 61, wherein said total number of transitions in said bit ordering exceeds a minimum said number of transitions by 1.

66. The method of claim 65, wherein M=3 and wherein said total number of transitions is 8.

67. The method of claim 65, wherein M=4 and wherein said total number of transitions is 16.

68. The method of claim 61, wherein said maximum number of transitions in said bit ordering is a minimum said maximum number of transitions.

69. The method of claim 68, wherein M=3 and wherein said maximum number of transitions is 3.

70. The method of claim 68, wherein M=4 and wherein said maximum number of transitions is 5.

71. The method of claim 61, wherein said minimum number of transitions in said bit ordering is a minimum said minimum number.

72. The method of claim 71, wherein said minimum number of transitions is 1.

73. The method of claim 61, wherein said bit ordering is such that all M bits have a common number of transitions.

74. The method of claim 73, wherein M=3 and wherein said common number is 3.

75. The method of claim 61, wherein said bit ordering is such that said number of transitions of any bit differs from said number of transitions of any other bit by at most 1.

76. The method of claim 75, wherein M=3 and wherein a maximum said number of transitions is 4 and a minimum said number of transitions is 3.

77. The method of claim 75, wherein M=4 and wherein a maximum said number of transitions is 5 and a minimum said number of transitions is 4.

78. A memory device comprising:

(a) a memory that includes K cells; and

(b) a controller operative to store N bits of data in said cells by programming each said cell with up to M=┌

N/K┐

of said bits according to a valid, nonserial bit ordering that satisfies a criterion selected from the group consisting of;

(i) a total number of transitions in said bit ordering is a minimum said number of transitions,

(ii) said total number of transitions in said bit ordering exceeds a minimum said number of transitions by 1,

(iii) a maximum said number of transitions in said bit ordering is a minimum said maximum number of transitions,

(iv) a minimum said number of transitions in said bit ordering is a minimum said minimum number of transitions,

(v) said bit ordering is such that all M bits have a common number of transitions, and

(vi) said bit ordering is such that a number of transitions of any bit differs from a number of transitions of any other bit by at most 1;

wherein M is at least 3.