Methods and systems for down-converting electromagnetic signals, and applications thereof

• US 20050202797A1
• Filed: 12/27/2004
• Published: 09/15/2005
• Est. Priority Date: 10/21/1998
• Status: Active Grant

• Current Assignee: ParkerVision, Inc.
• Original Assignee: ParkerVision, Inc.
• Inventors: Cook, Robert W., Bultman, Michael J., Sorrells, David F., Moses, Charley D. Jr., Looke, Richard C.
• Granted Patent: US 7,194,246 B2
• Time in Patent Office: Days
• US Class Current: 455/313
• CPC Class Codes: H03C 1/62 Modulators in which amplitude of carrier component in output is dependent upon strength of modulating signal, e.g. no carrier output when no modulating signal is present H03C1/28 - H03C1/34, H03C1/46, H03C1/48 take precedence
• CPC Class Codes: H03D 7/00 Transference of modulation from one carrier to another, e.g. frequency-changing H03D9/00, H03D11/00 take precedence; dielectric amplifiers, magnetic amplifiers, parametric amplifiers used as a frequency-changers H03F
• CPC Class Codes: H03D 7/1441 using field-effect transistors H03D7/145 takes precedence
• CPC Class Codes: H03D 7/1475 Subharmonic mixer arrangements
• CPC Class Codes: H04B 1/0025 using a sampling rate lower than twice the highest frequency component of the sampled signal for demodulation of angle-modulated signals H03D3/006
• CPC Class Codes: H04B 1/16 Circuits
• CPC Class Codes: H04B 1/28 the receiver comprising at least one semiconductor device having three or more electrodes
• CPC Class Codes: H04B 7/12 Frequency diversity
• CPC Class Codes: H04L 25/08 Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 27/00 Modulated-carrier systems
• CPC Class Codes: H04L 27/06 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 27/12 Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/14 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 27/148 using filters, including PLL-type filters
• CPC Class Codes: H04L 27/156 with demodulation using temporal properties of the received signal, e.g. detecting pulse width
• CPC Class Codes: H04L 27/2672 Frequency domain
• CPC Class Codes: H04L 27/3881 using sampling and digital processing, not including digital systems which imitate heterodyne or homodyne demodulation

Abstract

Methods, systems, and apparatuses for down-converting an electromagnetic (EM) signal by aliasing the EM signal are described herein. Briefly stated, such methods, systems, and apparatuses operate by receiving an EM signal and an aliasing signal having an aliasing rate. The EM signal is aliased according to the aliasing signal to down-convert the EM signal. The term aliasing, as used herein, refers to both down-converting an EM signal by under-sampling the EM signal at an aliasing rate, and down-converting an EM signal by transferring energy from the EM signal at the aliasing rate. In an embodiment, the EM signal is down-converted to an intermediate frequency (IF) signal. In another embodiment, the EM signal is down-converted to a demodulated baseband information signal. In another embodiment, the EM signal is a frequency modulated (FM) signal, which is down-converted to a non-FM signal, such as a phase modulated (PM) signal or an amplitude modulated (AM) signal.

Claims

1. A circuit for frequency down-converting an in-phase/quadrature-phase (I/Q) signal, comprising:

a first universal frequency translation module accepting the I/Q signal;

a second universal frequency translation module accepting the I/Q signal; and

a splitter circuit accepting a local oscillating signal, wherein said splitter circuit comprises;

a first inverter circuit comprising one or more inverters;

a second inverter circuit comprising two or more inverters;

a first flip-flop electrically coupled to said first inverter circuit; and

a second flip-flop electrically coupled to said second inverter circuit, wherein

said first inverter circuit receives said local oscillating signal and said first flip-flop outputs an “

I-channel”

oscillating signal,

said second inverter circuit receives said local oscillating signal and said second flip-flop outputs a “

Q-channel”

oscillating signal, wherein

said “

I-channel”

oscillating signal is electrically coupled to said first universal frequency translation module, and

said “

Q-channel”

oscillating signal is electrically coupled to said second universal frequency translation module,

thereby causing said first universal frequency translation module to output the down-converted “

I”

signal, and said second universal frequency translation module to output the down-converted “

Q”

signal.

2. The circuit of claim 1, wherein said first inverter circuit is comprised of an odd number of inverters, and said second inverter circuit is comprised of an even number of inverters.

3. The circuit of claim 1, wherein said “

I-channel”

oscillating signal has an “

I-channel”

frequency and an “

I-channel”

phase and said “

Q-channel”

oscillating signal has a “

Q-channel”

frequency and a “

Q-channel”

phase, wherein said “

Q-channel”

frequency is substantially equal to said “

I-channel”

frequency and said “

Q-channel”

phase is substantially 90°

out of phase with said “

I-channel”

phase.

4. The circuit of claim 3, wherein said “

I-channel”

frequency is substantially equal to a sub-harmonic of a frequency of the “

I/Q”

signal.

5. The circuit of claim 1, wherein said first universal frequency translation module, said second universal frequency translation module, and said splitter circuit are fabricated in a complementary metal oxide semiconductor (CMOS) circuit.

6. A method for down-converting an in-phase/quadrature-phase (I/Q) signal, comprising the steps of:

(1) delaying an oscillating signal by a first phase amount creating a first delayed oscillating signal;

(2) delaying said oscillating signal by a second phase amount creating a second delayed oscillating signal;

(3) routing said first delayed oscillating signal to a first flip-flop circuit, thereby creating an “

I-channel”

oscillating signal;

(4) routing said second delayed oscillating signal to a second flip-flop circuit, thereby creating a “

Q-channel”

oscillating signal;

(5) routing said “

I-channel”

oscillating signal to a first energy transfer module, said first energy transfer module also accepting the I/Q signal, to thereby generate a down-converted “

I”

signal;

(6) routing said “

Q-channel”

oscillating signal to a second energy transfer module said second energy transfer module also accepting the I/Q signal, to thereby generate a down-converted “

Q”

signal.

7. The method of claim 6, wherein said “

I-channel”

oscillating signal has an “

I-channel”

frequency and an “

I-channel”

phase and said “

Q-channel”

oscillating signal has a “

Q-channel”

frequency and a “

Q-channel”

phase, wherein said “

I-channel”

frequency and said “

Q-channel”

frequency are substantially equal to said frequency of said oscillating signal and said “

Q-channel”

phase is substantially 90°

out of phase with said “

I-channel”

phase.

8. A circuit for down-converting an electromagnetic signal, comprising:

an energy transfer module and an energy storage module, said energy transfer module sampling the electromagnetic signal at an energy transfer rate to obtain sampled energy, said sampled energy being stored by said energy storage module, a down-converted signal being generated from said sampled energy, wherein

said energy transfer module comprises;

transistors coupled together, said transistors having a common first port, a common second port, and a common control port, wherein the electromagnetic signal is accepted at said common first port and said sampled energy is present at said common second port, and further wherein said common control port accepts a control signal, said control signal having a control frequency that is substantially equal to said energy transfer rate.