Method for forming a low leakage contact in a CMOS imager

• US 20050205905A1
• Filed: 05/13/2005
• Published: 09/22/2005
• Est. Priority Date: 12/08/1998
• Status: Active Grant

• Current Assignee: Howard E. Rhodes
• Original Assignee: Howard E. Rhodes
• Inventors: Rhodes, Howard E.
• Granted Patent: US 7,224,009 B2
• Time in Patent Office: Days
• US Class Current: 257/292
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof

Abstract

An imaging device formed as a CMOS semiconductor integrated circuit includes a doped polysilicon contact line between the floating diffusion region and the gate of a source follower output transistor. The doped polysilicon contact line in the CMOS imager decreases leakage from the diffusion region into the substrate which may occur with other techniques for interconnecting the diffusion region with the source follower transistor gate. Additionally, the CMOS imager having a doped polysilicon contact between the floating diffusion region and the source follower transistor gate allows the source follower transistor to be placed closer to the floating diffusion region, thereby allowing a greater photo detection region in the same sized imager circuit.

Claims

1-13. -13. (canceled)

14. An imaging device comprising:

a substrate;

a photosensitive area within said substrate for accumulating photo-generated charge in said area;

a floating diffusion region in said substrate for receiving charge from said photosensitive area;

a readout circuit comprising at least an output transistor formed in said substrate;

an insulating layer formed over said substrate;

doped polysilicon plugs formed in said insulating layer which contact said floating diffusion region and said output transistor; and

an interconnector formed over said insulating layer which connects said doped polysilicon plugs.

22. The imaging device according to claim 14, wherein said substrate includes an n-type implant of arsenic or phosphorous into said substrate at a dopant concentration of about 1.0×

10¹² to about 3.0×

10¹³ ions/cm².

23. The imaging device according to claim 14, including a contact between said polysilicon plug and said floating diffusion region formed by diffusion of dopants from said doped polysilicon plug into said diffusion region.

15-21. -21. (canceled)

24-45. -45. (canceled)

46. An imaging device comprising

a semiconductor integrated circuit substrate;

a photosensitive device formed on said substrate for accumulating photo-generated charge in an underlying region of said substrate;

a floating diffusion region in said substrate for receiving said photo-generated charge;

a readout circuit comprising at least an output transistor formed in said substrate;

an insulating layer formed over said substrate; and

doped polysilicon plugs formed in said insulating layer which contact said floating diffusion region and said output transistor; and

an interconnector formed over said insulating layer which connects said doped polysilicon plugs.

52. The imaging device according to claim 46, including a contact between said doped polysilicon plug and said floating diffusion region formed by diffusion of dopants from said doped polysilicon plug into said diffusion region.

53. The imaging device according to claim 46, further comprising at least one charge transfer device for transferring charge from said photosensitive area to said floating diffusion region in accordance with a control signal applied to a control terminal.

54. The imaging device according to claim 46, wherein said doped polysilicon plugs are a composite layered doped polysilicon/barrier metal silicide/metal structure.

55. The imaging device according to claim 46, wherein said substrate includes an n-type implant of arsenic or phosphorous into said substrate at a dopant concentration of about 1.0×

10¹² to about 3.0×

10¹³ ions/cm².

47-51. -51. (canceled)

56-64. -64. (canceled)

65. A method for generating output signals corresponding to an image focused on a sensor array having rows and columns of pixel sensors, the method comprising the steps of:

sequentially activating each row of sensors of said array for a period of time;

detecting a first voltage at a node of an activated sensor, which corresponds to collected charges produced by a detected image;

resetting the voltage of said node to a first predetermined voltage by a reset transistor;

transferring image generated electrical charges collected by said activated sensor to said node, the voltage at the node changing from a first reset voltage to a second voltage corresponding to the respective amount of transferred electrical charges;

detecting the second voltage at the node of said activated sensor; and

generating an output signal by transferring charge from said node of said activated sensor to an output transistor via a doped polysilicon contact formed on an insulating layer.

71. The method for generating an output signal according to claim 65, wherein a contact between said buried conductor and said node is formed by diffusion of dopants from said doped polysilicon contact into said diffusion region.

73. The method for generating an output signal according to claim 65, wherein said substrate includes an n-type implant of arsenic or phosphorous into said substrate at a dopant concentration of about 1.0×

10¹² to about 3.0×

10¹³ ions/cm².

66-70. -70. (canceled)

72. (canceled)

74-75. -75. (canceled)

76. An imaging system for generating output signals based on an image focused on the imaging system, the imaging system comprising:

a plurality of pixel cells arranged into an array of rows and columns, each pixel cell being operable to generate a voltage at a diffusion node corresponding to detected light intensity by the cell;

a row decoder having a plurality of control lines connected to the cell array, each control line being connected to the cells in a respective row, wherein the row decoder is operable to activate the cells in a row; and

a plurality of output circuits each including a respective output transistor, each output circuit being connected to a respective cell of said array, each circuit being operable to store voltage signals received from a respective cell and to provide a cell output signal; and

a plurality of doped polysilicon contacts for respectively interconnecting a diffusion node of a pixel cell with a gate of a source follower transistor.

84. The imaging system according to claim 76, wherein said substrate includes an n-type implant of arsenic or phosphorous into said substrate at a dopant concentration of about 1.0×

10¹² to about 3.0×

10 ¹³ ions/cm².

77-83. -83. (canceled)

85-89. -89. (canceled)

90. A processing system comprising:

(i) a processor; and

(ii) a CMOS imaging device coupled to said processor and including;

a substrate;

a photosensitive area within said substrate for accumulating photo-generated charge in said area;

a floating diffusion region in said substrate for receiving charge from said photosensitive area;

a readout circuit comprising at least an output transistor formed in said substrate;

an insulating layer formed over said substrate; and

a doped polysilicon conductor formed at least partially within said insulating layer for interconnecting said floating diffusion region with said output transistor.

97. The system according to claim 90, wherein said substrate includes an n-type implant of arsenic or phosphorous into said substrate at a dopant concentration of about 1.0×

10¹² to about 3.0×

10¹³ ions/cm².

91-96. -96. (canceled)

98-102. -102. (canceled)

103. A processing system comprising:

(i) a processor; and

(ii) a CMOS imaging device coupled to said processor and including;

a substrate;

a photosensitive area within said substrate for accumulating photogenerated charge in said area;

a floating diffusion region in said substrate for receiving charge from said photosensitive area;

a readout circuit comprising at least an output transistor formed in said substrate;

an insulating layer formed over said substrate;

doped polysilicon plugs formed in said insulating layer which contact said floating diffusion region and said output transistor; and

an interconnector formed over said insulating layer which connects said doped polysilicon plugs.

112. The system according to claim 103, wherein said substrate includes an n-type implant of arsenic or phosphorous into said substrate at a dopant concentration of about 1.0×

10¹² to about 3.0×

10¹³ ions/cm².

104-111. -111. (canceled)

113-149. -149. (canceled)