Multi-layer wiring structure with dummy patterns for improving surface flatness

• US 20050212136A1
• Filed: 07/26/2004
• Published: 09/29/2005
• Est. Priority Date: 03/29/2004
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Otsuka, Satoshi, Karasawa, Toshiyuki
• Granted Patent: US 7,161,248 B2
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A first area, a ring shape second area surrounding the first area, and a third area surrounding the second area are defined on the surface of a support substrate. A first wiring layer is disposed above the support substrate. A wiring is formed in the third area, dummy patterns being formed in the second area, and conductive patterns are not formed in the first area. A functional element is disposed above the first wiring layer and in the first area.

Claims

1. A multi-layer wiring structure comprising:

a support substrate, on a surface of which a first area, a loop shape second area surrounding the first area, and a third area surrounding the second area are defined;

a first wiring layer disposed above the support substrate, a wiring being formed in the third area, dummy patterns being formed in the second area, and conductive patterns are not formed in the first area; and

a functional element disposed above the first wiring layer and in the first area.

2. The multi-layer wiring structure according to claim 1, wherein the second area includes a first sub area on a first area side and a second sub area outside of the first sub area, and a pattern density of the first sub area is lower than a pattern density of the second sub area.

3. The multi-layer wiring structure according to claim 1, further comprising a second wiring layer disposed between the first wiring layer and the functional element, conductive patterns are not formed in the first and second areas of the second wiring layer or only a wiring directly connected to the functional element is formed in the first and second areas of the second wiring layer.

4. The multi-layer wiring structure according to claim 1, further comprising at least one third wiring layer disposed between the support substrate and the first wiring layer, conductive patterns being formed in the first area of both the first wiring layer and the third wiring layer, and dummy patterns being formed in the second area of the first wiring layer and the third wiring layer.

5. The multi-layer wiring structure according to claim 1, wherein the first area is a loop shape area, the multi-layer wiring structure further comprises a fourth area surrounded by the first area, the functional element is an inductor disposed not in the fourth area but in the first area, and dummy patterns are formed in the fourth area of the first wiring layer.

6. The multi-layer wiring structure according to claim 5, further comprising at least one third wiring layer disposed between the support substrate and the first wiring layer, and dummy patterns are formed in the fourth area of both the first wiring layer and the third wiring layer.

7. The multi-layer wiring structure according to claim 6, wherein conductive patterns are not formed in the first area of both the first wiring layer and the third wiring layer, and dummy patterns are formed in the second area of the first wiring layer and the third wiring layer.

8. The multi-layer wiring structure according to claim 1, further comprising:

a semiconductor active device formed in the third area and on the surface of the support substrate; and

an element isolation insulating film inclusively covering the first and second areas of the surface of the support substrate.

9. The multi-layer wiring structure according to claim 1, wherein an outer periphery of the first area forms a square or a rectangle, and a width of the second area is at least 0.3 times as large as a length of a side of the square or a short side of the rectangle.

10. A multi-layer wiring structure comprising:

a support substrate having a loop shape first area, a second area surrounding the first area, and a third area surrounded by the first area, respectively defined on a surface of the support substrate;

a first wiring layer disposed above the support substrate, a wiring being formed in the second area, dummy patterns being formed in the third area, and conductive patterns are not formed in the first area; and

a functional element disposed above the first wiring layer and in the first area.

11. The multi-layer wiring structure according to claim 10, further comprising a second wiring layer disposed between the first wiring layer and the functional element, conductive patterns are not formed in the first and third areas of the second wiring layer or only a wiring directly connected to the functional element is formed in the first area of the second wiring layer.

12. The multi-layer wiring structure according to claim 10, further comprising at least one third wiring layer disposed between the support substrate and the first wiring layer, conductive patterns are not formed in the first area of the first wiring layer and the third wiring layer, and dummy patterns are formed in the third area of the first wiring layer and the third wiring layer.

13. The multi-layer wiring structure according to claim 10, further comprising:

a semiconductor active device formed in the second area and on the surface of the support substrate; and

an element isolation insulating film inclusively covering the first and third areas of the surface of the support substrate.