Apparatus and method for performing initial cell search in wireless communication systems

• US 20050221848A1
• Filed: 05/16/2005
• Published: 10/06/2005
• Est. Priority Date: 06/22/2001
• Status: Abandoned Application

• Current Assignee: Interdigital Technology Corporation (InterDigital, Inc.)
• Original Assignee: Interdigital Technology Corporation (InterDigital, Inc.)
• Inventors: Guccione, Louis J., Chitrapu, Prabhakar R., Bednarz, Andrew F.
• Application Number:
  US11/129,789
• Publication Number:
  US 20050221848A1
• Time in Patent Office: Days
• US Class Current: 455/502
• CPC Class Codes: H04B 1/70735 Code identification H04B1/7083 takes precedence
• CPC Class Codes: H04B 1/7083 Cell search, e.g. using a three-step approach

Abstract

The system and method of the present invention establishes a communication link between a user equipment (UE) and a base station in a communication system having a plurality of base stations which each transmit a common primary synchronization code (PSC) in a primary synchronization channel in conjunction with a base station specific secondary synchronization code (SSC) within a system frame, which receives with the UE an input signal including the PSC and SSC from at least one of the base stations. The UE analyzes the input signal to detect any received PSCs within a selected time period which has duration corresponding to the length of a system frame and determining a relative location of a strongest PSC within the selected time period. The input signal is then processed to remove the PSC from at least the determined PSC location. A secondary synchronization code (SSC) is then detected for the determined location from the processed signal. The communication link is then established using the detected SSCs.

Claims

1. A user equipment (UE) configured to perform initial cell search in a wireless communication system having a plurality of base stations, each base station transmitting a common primary synchronization code (PSC) in a primary synchronization channel in conjunction with a base station specific secondary synchronization code (SSC) at a different time within a system frame, said UE receiving an input signal including the PSC and SSC from at least one of the base stations;

said UE comprising;

a step one processor for detecting PSCs within a selected time frame in said received input signal and determining a maximum PSC location, which corresponds to the maximum PSC value detected within the frame, and producing an output complex correlation value;

a cancellation device for subtracting the PSC value at the maximum PSC location within the frame to enhance detection of the SSC;

a step two processor, coupled to the step one processor and the cancellation device, configured to determine a scrambling code group number for the cell and a frame timing offset value for locating the frame boundary; and

a step three processor, coupled to the step two processor, configured to determine the scrambling code of the cell.

2. The UE of claim 1 wherein said cancellation device uses interference cancellation to remove said PSC from said input signal.

3. The UE of claim 1 wherein the step two processor comprises:

a correlator configured to correlate the input signal with a code sequence corresponding to the maximum PSC location.

4. The UE of claim 3 wherein the step two processor further comprises:

a device configured to correlate the input signal with N SSCs outputting a set of N complex correlation values t, where N is an integer greater than one.

5. The UE of claim 4 wherein the step two processor further comprises:

a phase estimator device configured to determine a phase estimate of the complex correlation value from the step one processor; and

a derotation device configured to derotate the set of N complex correlation values using the phase estimate.

6. The UE of claim 5 wherein the step two processor further comprises:

an accumulator configured to coherently add the derotated set of N correlation values at a predetermined period for a predetermined number of iterations, producing a set of decision variables; and

a decision device configured to select a maximum decision variable, from which the scrambling code group number for the cell and the frame timing offset value are determined.

7. The UE of claim 1 wherein the step three processor comprises:

a step three correlation device configured to produce step three correlation values that are the maximum correlation of the input signal correlated with midambles associated with the code group;

a step three accumulation device configured to accumulate the step three correlation values over a predetermined number of system frames producing step three decision variables; and

a step three decision device configured to determine the maximum step three decision variable from which the basic midamble for the cell and the scrambling code of the cell is determined.

8. The UE of claim 7 further comprising a second cancellation device coupled between the step two and step three processors configured to subtract the SSCs from the input signal to enhance detection of the code group number and midambles associated with the code group.