Bump for semiconductor package, semiconductor package applying the bump, and method for fabricating the semiconductor package

• US 20050224991A1
• Filed: 10/29/2004
• Published: 10/13/2005
• Est. Priority Date: 04/08/2004
• Status: Active Grant

• Current Assignee: Nepes Co., Ltd.
• Original Assignee: Nepes Co., Ltd.
• Inventors: Yeo, Yong-Woon
• Granted Patent: US 7,170,170 B2
• Time in Patent Office: Days
• US Class Current: 257/781
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/11472 Profile of the lift-off mask
• CPC Class Codes: H01L 2224/11474 Multilayer masks
• CPC Class Codes: H01L 2224/13017 being non uniform along the bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/29111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/83851 being an anisotropic conductive adhesive
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07811 : Extrinsic, i.e. with electrical conductive fillers

Abstract

The present invention discloses a bump for a semiconductor package, a semiconductor package applying the bump, and a method for fabricating the semiconductor package. As a second bump unit contacting an electrode terminal of a PCB has a smaller width than a first bump unit contacting an electrode pad of a semiconductor chip through a metal adhering layer, even if a pitch between the electrode pads of the semiconductor chip does not correspond to the pitch between the electrode terminals of the PCB, contact reliability is improved by the bump. In addition, the bump does not contact lines adjacent to the electrode terminal of the PCB, thereby preventing a mis-operation of the semiconductor package. Accordingly, the pitch between the electrode pads of the semiconductor chip and the pitch between the bumps can be minimized.

Claims

1. A bump for a semiconductor package, comprising:

a metal adhering layer formed on the surface of a semiconductor chip;

a first bump unit formed on the metal adhering layer; and

a second bump unit formed on the first bump unit, a width of the second bump unit being smaller than that of the first bump unit.

2. The bump of claim 1, wherein an electrode pad of the semiconductor chip is selectively exposed by a protecting film, and the metal adhering layer is formed on the electrode pad of the semiconductor chip and extended from the upper portion of the electrode pad to the upper portion of the protecting film around the electrode pad.

3. The bump of claim 1, wherein the first and second bump units are composed of at least one selected from the group consisting of Au, Sn/37Pb, Sn/95Pb, Cu, Sn/Ag and Ni.

4. The bump of claim 1, wherein the first and second bump units are formed with the same height or different height.

5. The bump of claim 2, wherein the electrode pad of the semiconductor chip is composed of at least one selected from the group consisting of Ti, Al, Cr and Cu, or an alloy containing at least one selected from the group consisting of Ti, Al, Cr and Cu.

6. The bump of either claim 1 or 2, wherein the metal adhering layer is composed of a metal containing at least one selected from the group consisting of TiW, Ti, Cr, Ni, V, Bi, Cu and Au having an excellent wetting property to the electrode pad of the semiconductor chip.

7. The bump of claim 1, wherein the metal adhering layer is formed at a thickness of 100 to 20000 Å

.

8. The bump of claim 1, further comprising a solder cap formed on the top surface of the second bump unit.

9. The bump of claim 8, wherein the solder cap is composed of at least one selected from the group consisting of Pb/Sn, Sn/(5%)Pb and Sn/(2.5)Ag, or an alloy prepared by adding at least one selected from the group consisting of Ag, Au, Bi, Cu, In, Zn, and P to Sn or Pb.

10. The bump of claim 8, further comprising a diffusion barrier film formed on the surface of the copper bump and composed of at least one selected from the group consisting of Ni, V and P, or an alloy containing at least one selected from the group consisting of Ni, V and P.

11. The bump of claim 1, wherein the width of the second bump unit is smaller than that of the first bump unit by 10 to 150 mm.

12. A semiconductor package, comprising:

a semiconductor chip on which an electrode pad has been formed;

a protecting film formed on the surface of the semiconductor chip, for selectively exposing the electrode pad;

a metal adhering layer formed on the electrode pad, and extended from the upper portion of the electrode pad to the upper portion of the protecting film around the electrode pad;

a first bump unit formed on the metal adhering layer;

a second bump unit formed on the first bump unit, a width of the second bump unit being smaller than that of the first bump unit; and

a PCB on which an electrode terminal contacting the top surface of the second bump unit has been formed.

13. The semiconductor package of claim 12, wherein the top surface of the second bump unit and the electrode terminal of the PCB are thermocompression bonded and hardened to contact each other by the medium of a polymer containing anisotropic conductive particles.

14. The semiconductor package of claim 13, wherein the polymer containing anisotropic conductive particles is a liquid phase anisotropic conductive adhesive or a solid phase anisotropic conductive film quasi-hardened in a predetermined shape.

15. The semiconductor package of claim 13, wherein the polymer containing anisotropic conductive particles comprises a thermosetting resin or a thermosetting and thermoplastic resin as a major element, and also comprises spherical or angular conductive metal balls.

16. The semiconductor package of claim 15, wherein the conductive metal balls are composed of at least one selected from the group consisting of Au, Ni, Ag and Cu.

17. The semiconductor package of claim 15, wherein the conductive metal balls have a grain size of 0.5 to 10 mm.

18. The semiconductor package of claim 12, wherein the top surface of the second bump unit and the electrode terminal of the PCB contact each other through a solder cap formed on the top surface of the second bump unit.

19. A method for fabricating a semiconductor package, comprising the steps of:

forming a metal adhering layer on a semiconductor chip on which at least one electrode pad selectively exposed by a protecting film has been formed;

forming a first photosensitive photoresist on the metal adhering layer, and performing whole light exposure thereon;

forming a second photosensitive photoresist on the whole light exposed first photosensitive photoresist, and performing local light exposure thereon;

developing the second photosensitive photoresist and the first photosensitive photoresist;

forming a bump consisting of first and second bump units on the metal adhering layer exposed by developing the second photosensitive photoresist and the first photosensitive photoresist;

removing the second photosensitive photoresist and the first photosensitive photoresist;

etching the metal adhering layer exposed by removing the first photosensitive photoresist and the second photosensitive photoresist; and

making the electrode terminal of the PCB contact the top surface of the second bump unit.

20. The method of claim 19, wherein the bump consisting of the first bump unit and the second bump unit is formed according to electric electrolytic plating or electroless plating.

21. The method of claim 19, wherein the metal adhering layer is formed at a thickness of 100 to 20000 Å

according to sputtering, thermal deposition or electron beam deposition.

22. The method of claim 19, wherein the step for etching the metal adhering layer is performed according to wet etching using chemicals or dry etching using a physical method.

23. The method of claim 19, wherein the step for making the electrode terminal of the PCB contact the top surface of the second bump unit disposes a polymer containing anisotropic conductive particles between the second bump unit and the electrode terminal of the PCB, and performs thermocompression bonding and hardening thereon.

24. The method of claim 19, further comprising a step for forming a solder cap on the top surface of the second bump unit after forming the bump consisting of the first and second bump units.

25. The method of claim 24, wherein the solder cap formed on the top surface of the second bump unit and the electrode terminal of the PCB are compressed and bonded at a temperature ranging from 100 to 400°

C.

26. The method of claim 24, further comprising a step for forming a diffusion barrier layer on the surface of copper bump consisting of the first and second bump units.