Testing MEM device array

• US 20050231204A1
• Filed: 04/17/2004
• Published: 10/20/2005
• Est. Priority Date: 04/17/2004
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Martin, Eric T., Ghozeil, Adam
• Granted Patent: US 7,026,821 B2
• Time in Patent Office: Days
• US Class Current: 324/415
• CPC Class Codes: B81C 99/005 Test apparatus
• CPC Class Codes: G11C 29/54 Arrangements for designing test circuits, e.g. design for test [DFT] tools
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

A system of an embodiment of the invention includes an array of micro-electromechanical (MEM) device assemblies and a testing mechanism situated outside of the array of the MEM device assemblies. Each MEM device assembly includes a MEM device capable of being individually written to, but incapable of being electrically read. The testing mechanism tests each MEM device assembly for proper operation without directly reading the MEM device of the MEM device assembly.

Claims

1. A system comprising:

an array of micro-electromechanical (MEM) device assemblies, each MEM device assembly having a MEM device capable of being individually written to but incapable of being electrically read; and

,

a testing mechanism situated outside of the array of the MEM device assemblies to test each MEM device assembly for proper operation without directly reading the MEM device of the MEM device assembly.

2. The system of claim 1, wherein the testing mechanism is capable of verifying that an electrical path exists through each of the MEM device assemblies.

3. The system of claim 1, wherein the MEM device assemblies of the array are organized into columns and rows, and the testing mechanism is capable of verifying that each row of the MEM device assemblies is able to discharge each column of the MEM device assemblies upon the column of the MEM device assemblies having initially been charged.

4. The system of claim 1, wherein each MEM device assembly comprises:

the MEM device;

a first switch coupling a column control signal to the MEM device; and

,

a second switch coupling a clear voltage to the MEM device.

5. The system of claim 4, wherein each of the first switch and the second switch is a transistor.

6. The system of claim 4, wherein the MEM device of each MEM device assembly comprises at least one of:

a light modulation MEM device and a digital light device (DLD).

7. The system of claim 6, wherein the system is a projection system in which light is modulated by the array of MEM device assemblies in accordance with image data from an image source and subsequently projected from the system.

8. The system of claim 1, wherein the MEM device assemblies of the array are organized into columns and rows, the system further comprising:

a column control mechanism to select one or more of the columns of the MEM device assemblies; and

,

a row control mechanism to select one or more of the rows of the MEM device assemblies.

9. The system of claim 8, further comprising:

a column output mechanism to receive test results from the one or more columns of the MEM device assemblies as tested by the testing mechanism; and

,

a row output mechanism to receive test results from the one or more rows of the MEM device assemblies as tested by the testing mechanism.

10. The system of claim 8, wherein the testing mechanism is communicatively coupled to the column control mechanism and the row control mechanism to charge selected one or more of the columns of the MEM device assemblies through the column control mechanism and to charge selected one or more of the rows of the MEM device assemblies through the row control mechanism.

11. The system of claim 8, wherein each of the column control mechanism and the row control mechanism comprises a multiplexer.

12. A system comprising:

an array of nodes organized into rows and columns, each node having a micro-electromechanical (MEM) device incapable of being electrically read, a first switch coupling a column line to the MEM device and a second switch coupling a clear voltage to the MEM device; and

,

a testing mechanism situated outside of the array of nodes to test each node for proper operation by selecting a row and a column of the nodes in which the node is located to turn on the first and the second switches of the node and by verifying that an electrical path exists from the column, and through the first and the second switches, to the clear voltage.

13. The system of claim 12, wherein each row of the nodes comprises a first row line connected to a control of the first switch of each node of the row, and a second row line connected to a control of the second switch of each node of the row.

14. The system of claim 12, wherein each column of the nodes comprises a column line coupled to an input of the first switch of each node of the column.

15. The system of claim 12, wherein the first switch of each node has an input coupled to a column of the nodes in which the node is located, and the second switch of each node has an output coupled to a clear voltage.

16. The system of claim 12, wherein the testing mechanism further is to test each node for proper operation by verifying that each row of the nodes is able to discharge each column of the nodes to a clear voltage upon the column of the nodes having initially been charged.

17. The system of claim 12, wherein the system further comprises:

a column control mechanism by which the testing mechanism is to select one or more of the columns of the nodes;

a row control mechanism by which the testing mechanism is to select one or more of the rows of the nodes;

a column output mechanism to receive test results from the one or more columns of the nodes as tested by the testing mechanism; and

,

a row output mechanism to receive test results from the one or more rows of the nodes as tested by the testing mechanism.

18. The system of claim 12, wherein the system is a projection system in which light is modulated by the array of MEM device assemblies in accordance with image data from an image source and subsequently projected from the system.

19. A system comprising:

an array of micro-electromechanical (MEM) device assemblies, each MEM device assembly including a MEM device capable of being individually written to but incapable of being electrically read; and

,

means for testing each MEM device assembly for proper operation without directly reading the MEM device of the MEM device assembly.

20. The system of claim 19, wherein the means is further for verifying that an electrical path exists through each of the MEM device assemblies.

21. The system of claim 19, wherein the MEM device assemblies of the array are organized into columns and rows, and the means is further for verifying that each row of the MEM device assemblies is able to discharge each column of the MEM device assemblies to a clear voltage upon the column of the MEM device assemblies having initially been charged.

22. The system of claim 19, wherein the system is a projection system in which light is modulated by the array of MEM device assemblies in accordance with image data from an image source and subsequently projected from the system.

23. A method comprising:

charging a row of an array of micro-electromechanical (MEM) device assemblies organized into rows and columns to turn on a first transistor and a second transistor of each MEM device assembly of the row;

charging a column of the array of MEM device assemblies;

verifying proper operation of the one MEM device assembly by confirming that an electrical path exists from the column, through the first transistor of the one MEM device assembly, through the second transistor of the one MEM device assembly, and to a clear voltage,

wherein a source of the first transistor of each MEM device assembly is connected to a column of the array, a drain of the first transistor of the MEM device assembly is connected to a drain of the second transistor of the MEM device assembly, and a source of the second transistor of the MEM assembly is connected to the clear voltage.

24. The method of claim 23, further comprising repeating the method for each successive column of the columns of the array and for each successive row of the rows of the array.

25. A method comprising:

turning on one or more columns of an array of micro-electromechanical (MEM) device assemblies organized into rows and columns to charge the column;

verifying that the one or more columns of the array of MEM device assemblies properly received the charge;

turning off the one or more columns of the array of MEM device assemblies, such that a charge capacitively remains on each MEM device assembly of the one or more columns;

turning on a first row line of a row of the array of MEM device assemblies to turn on a first transistor of each MEM device assembly of the row;

turning on a second row line of the row of the array of MEM device assemblies to turn on a second transistor of each MEM device assembly of the row; and

,

verifying that the one or more columns of the array of MEM device assemblies properly discharged the charge,

wherein a source of the first transistor of each MEM device assembly is connected to a column of the array, a drain of the first transistor of the MEM device assembly is connected to a drain of the second transistor of the MEM device assembly, and a source of the second transistor of the MEM assembly is connected to a clear voltage.

26. The method of claim 26, further comprising repeating the method for each successive column of the columns of the array and for each successive row of the rows of the array.

27. A method comprising:

providing, for each of an array of nodes organized into rows and columns, a micro-electromechanical (MEM) device incapable of being electrically read, a first transistor having a drain coupled to the MEM device, and a second transistor having a drain coupled to the MEM device; and

,

situating a testing mechanism outside of the array of nodes that is capable of testing each node for proper operation by selecting a row and a column of the nodes in which the node is located to turn on the first and the second transistors of the node and by verifying that an electrical path exists from the column, through the first and the second transistors, and to a clear voltage.

28. The method of claim 27, wherein the testing mechanism further capable of testing each node for proper operation by verifying that each row of the nodes is able to discharge each column of the nodes to the clear voltage upon the column of the nodes having initially been charged.