Nonvolatile ferroelectric memory device with split word lines

• US 20050237784A1
• Filed: 06/28/2005
• Published: 10/27/2005
• Est. Priority Date: 08/08/2002
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Kang, Hee-Bok
• Granted Patent: US 7,012,851 B2
• Time in Patent Office: Days
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out

Abstract

The present invention relates to a memory device; and, more particularly, to a cell array of a nonvolatile ferroelectric memory device and an apparatus and a method for driving such a cell array. The nonvolatile ferroelectric memory device according to the present invention includes: a cell array region having first and second cell array blocks which are adjacent to each other and independently operate; a first drive region being adjacent to the first cell array block in the cell array region in order to drive first split words line which operate as plate lines of the first cell array block and word lines of the second cell array block; and a second drive region being adjacent to the second cell array block in the cell array region in order to drive first split word lines which operate as plate lines of the second cell array block and word lines of the first cell array block, wherein each of the first and second drive regions includes a plurality of split word line drivers and wherein each of the split word line drivers is connected to the plate lines of the first and second cell array blocks correspondent thereto.

Claims

1-15. -15. (canceled)

16. A nonvolatile ferroelectric memory device comprising:

first and second cell array blocks which independently operate in a split word line structure, wherein each of the first to fourth cell array blocks has a hierarchical bit line structure having a plurality of local bit lines correspondent to each of columns and a global bit line which is selectively connected to one of the plurality of the local bit lines by a plurality of switching transistors;

driving means for driving a split word line in the split word line structure, wherein the driving means includes;

an output terminal connected to the split word line;

decoding means for receiving a plurality of row address signals and activating the split word line;

pull-down means for carrying out a pull-down operation at the output terminal when the split word line are nonactivated;

pull-down control means for controlling the pull-down means in response to an output signal from the decoding means and an external control signal;

pull-up means for supplying a pumping voltage to the output terminal; and

pull-up control means for controlling the pull-up means by applying the output signal from the decoding means to the pull-up means in response to word line control signal.

17. The nonvolatile ferroelectric memory device recited as in claim 16, wherein the pull-up control means is a switching transistor having a gate to which the word line control signal is applied.

18-23. -23. (canceled)

24. A nonvolatile ferroelectric memory device comprising:

first and second cell array blocks which independently operate in a split word line structure, wherein each of the first to fourth cell array blocks has a hierarchical bit line structure having a plurality of local bit lines correspondent to each of columns and a global bit line which is selectively connected to one of the plurality of the local bit lines by a plurality of switching transistors;

driving means for driving a split word line in the split word line structure, wherein the driving means includes;

an output terminal connected to a plate line of the first cell array block;

decoding means for receiving a plurality of row address signals and activating the plate line of the first cell array block;

pull-down means for carrying out a pull-down operation at the output terminal when the plate line of the first cell array block are nonactivated;

pull-down control means for controlling the pull-down means in response to an output signal from the decoding means and an external control signal;

pull-up means for supplying a pumping voltage to the output terminal; and

pull-up control means for controlling the pull-up means by applying the output signal from the decoding means to the pull-up means in response to word line control signal.

25-30. -30. (canceled)