Low power A/D converter

• US 20050240113A1
• Filed: 06/30/2005
• Published: 10/27/2005
• Est. Priority Date: 11/05/2001
• Status: Active Grant

• Current Assignee: Cameron Incorporated (Schlumberger NV)
• Original Assignee: Cameron Incorporated (Schlumberger NV)
• Inventors: Ostroff, Alan H.
• Granted Patent: US 7,623,920 B2
• Time in Patent Office: Days
• US Class Current: 600/510
• CPC Class Codes: H03M 1/48 Servo-type converters
• CPC Class Codes: H03M 1/56 Input signal compared with linear ramp

Abstract

A comparator is arranged to compare a series of analog voltage signal samples on a first capacitor with a voltage on a second capacitor which is linearly increased or decreased to equal the sample value. The comparator'"'"'s single output freezes the count of the counter at counts which are proportional to the voltage of the respective samples. In this manner, analog to digital conversion can be accomplished using a single line between the analog and digital sides of a circuit, thereby reducing parasitic capacitance.

Claims

1. A method of cardiac signal analysis comprising:

capturing an electrical signal between implanted electrodes;

receiving the electrical signal on a first chip carrying a plurality of analog components;

sampling the electrical signal to create a first sample;

generating an output from the first chip by comparing the first sample to a stored sample;

receiving the output from the first chip on a second chip; and

generating a digital signal on the second chip indicative of the amplitude of the captured electrical signal.

2. The method of claim 1, wherein the step of generating an output from the first chip includes comparing the first sample to the stored sample using a comparator.

3. The method of claim 2, wherein the output from the first chip is the output from the comparator.

4. The method of claim 2, wherein:

the stored sample is stored using capacitor means for holding charge;

if a voltage on the capacitor means is different from the first sample, an equalizing circuit changes the charge stored on the capacitor means until the voltage on the capacitor means is substantially the same as the first sample; and

the output from the first chip indicates a duration of time that elapses while the equalizing circuit changes the charge stored on the capacitor means.

5. The method of claim 4, wherein the equalizing circuit comprises:

a charging circuit for increasing the charge on the capacitor means;

a discharging circuit for decreasing the charge on the capacitor means; and

switches controlling whether the charging circuit and the discharging circuit are coupled to the capacitor means.

6. The method of claim 1, wherein the second chip includes a counter having an up/down input, wherein the output from the first chip is coupled to the up/down input.

7. The method of claim 1, wherein the first chip comprises primarily analog circuitry and the second chip comprises primarily digital circuitry.

8. The method of claim 1, wherein a clock signal is generated and used on both the first chip and the second chip to coordinate operations of the first chip and the second chip.

9. An implantable medical device comprising at least first and second implantable electrodes and operational circuitry including a first chip and a second chip, the operational circuitry configured to perform a method of cardiac signal analysis comprising:

capturing an electrical signal between the implantable electrodes;

receiving the electrical signal on the first chip;

sampling the electrical signal to create a first sample;

generating an output from the first chip by comparing the first sample to a stored sample;

receiving the output from the first chip on the second chip; and

generating a digital signal on the second chip indicative of the amplitude of the captured electrical signal.

10. The implantable medical device of claim 9, wherein the operational circuitry is configured such that the step of generating an output from the first chip includes comparing the first sample to the stored sample using a comparator.

11. The implantable medical device of claim 10, wherein the operational circuitry is configured such that the output from the first chip is the output from the comparator.

12. The implantable medical device of claim 10, wherein the first chip comprises capacitor means for holding charge and an equalizing circuit and the operational circuitry is configured such that:

the stored sample is stored using the capacitor means;

if a voltage on the capacitor means is different from the first sample, the equalizing circuit changes the charge stored on the capacitor means until the voltage on the capacitor means is substantially the same as the first sample; and

the output from the first chip indicates a duration of time that elapses while the equalizing circuit changes the charge stored on the capacitor means.

13. The implantable medical device of claim 12, wherein the equalizing circuit comprises:

a charging circuit for increasing the charge on the capacitor means;

a discharging circuit for decreasing the charge on the capacitor means; and

switches controlling whether the charging circuit and the discharging circuit are coupled to the capacitor means.

14. The implantable medical device of claim 9, wherein the second chip includes a counter having an up/down input, wherein the output from the first chip is coupled to the up/down input.

15. The implantable medical device of claim 9, wherein the first chip comprises primarily analog circuitry and the second chip comprises primarily digital circuitry.

16. The implantable medical device of claim 9, further comprising a clock, the clock generating a clock signal that is delivered to both the first chip and the second chip.

17. A method of cardiac signal analysis comprising:

capturing a cardiac signal from electrodes implanted in a patient;

sampling a first sample related to a magnitude of the captured signal;

generating an output having a duration and a sign, the duration indicative of an magnitude of difference between the first sample and a previous sample and the sign indicative of a direction of difference between the first sample and a previous sample;

receiving the output at a counter and generating a digital output indicative of the magnitude of the first sample.

18. The method of claim 17, wherein the output is generated from analog circuitry on a first chip and the counter is disposed on a second chip, the method further comprising conveying the output from the first chip to the second chip.

19. The method of claim 17, wherein the output is generated from a comparator, the comparator having a first input and a second input, the first input receiving a signal related to the first sample magnitude and the second input receiving a signal generated as follows:

at a first time, the second input receives a signal related to the previous sample magnitude;

at a second time, the second input receives a signal approximating the first sample magnitude; and

, during a time period between the first time and the second time;

if the previous sample magnitude is greater than the first sample magnitude, the second input receives a signal that decreases in magnitude;

or

if the previous sample magnitude is less than the first sample magnitude, the second input receives a signal that increases in magnitude.

20. The method of claim 19, wherein:

the second input is coupled to capacitor means;

the capacitor means is selectively coupled via a first switch to a charging circuit and via a second switch to a discharging circuit; and

the output from the comparator is used to selectively close one of the first switch or the second switch during the time period between the first time and the second time.