Integrated circuits with persistent data storage

• US 20050242196A1
• Filed: 06/14/2005
• Published: 11/03/2005
• Est. Priority Date: 05/31/2001
• Status: Active Grant

• Current Assignee: RUIZHANG TECHNOLOGY LIMITED COMPANY
• Original Assignee: Alien Technology Corporation
• Inventors: Stewart, Roger G., Rolin, John
• Granted Patent: US 7,364,084 B2
• Time in Patent Office: Days
• US Class Current: 235/487
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06K 19/07381 with deactivation or otherwise incapacitation of at least a part of the circuit upon detected tampering

Abstract

The circuitry introduced in this invention selectively slows down the functioning of an electronic circuit by maintaining a particular state for a prolonged period of time. This circuitry is used not only to achieve the desired effect in maintaining security from electronic thieves trying to circumvent codes but also in other applications such as enabling a circuit to continue to function in the event of a brief loss of power. For example, in an RFID system, if a reader is frequency hopping, a tag loses power for as long as about 400 milliseconds when the reader changes to other frequencies. In a preferred embodiment, the disclosed circuitry is used in conjunction with a destruct sequence.

Claims

1. A radio frequency identification (RFID) circuit with persistent data storage, comprising:

a transistor coupled to an input voltage line;

a dielectric charge storage portion coupled to the transistor for storing a dielectric capacitance; and

a junction capacitance portion coupled to the transistor for storing a junction capacitance;

wherein the dielectric capacitance is at least 10 times greater than the junction capacitance.

2. The circuit as recited in claim 1, wherein the dielectric capacitance of the charge storage portion is at least 100 times greater than a junction capacitance of the junction capacitance portion.

3. The circuit as recited in claim 1, wherein a time constant of the dielectric charge storage portion is greater than 100 seconds, wherein a time constant of the junction capacitance portion is less than 1 second.

4. The circuit as recited in claim 1, further comprising at least one inverter on the input voltage line.

5. The circuit as recited in claim 1, further comprising three or more inverters on the input voltage line.

6. The circuit as recited in claim 1, wherein the charge storage portion is a dielectric capacitor.

7. The circuit as recited in claim 1, wherein the transistor is a PMOS transistor.

8. The circuit as recited in claim 1, wherein the transistor is an NMOS transistor.

9. The circuit as recited in claim 1, wherein the circuit is an extended duration one-shot circuit.

10. The circuit as recited in claim 1, wherein an extended time constant one-shot is provided independent of power supply.

11-21. -21. (canceled)

22. A circuit with persistent data storage, comprising:

at least one inverter on an input voltage line;

a transistor coupled to the at least one inverter;

a dielectric charge storage portion coupled to the transistor for storing a dielectric capacitance; and

a junction capacitance portion coupled to the transistor for storing a junction capacitance;

wherein the dielectric capacitance is at least 10 times greater than the junction capacitance.

23. A one shot circuit having a timing interval that is maintained constant independent of power fluctuations that occur during the timing interval.

24. The circuit as recited in claim 23, wherein the circuit forms a portion of a RFID device.

25. A one-shot circuit having a timing interval of greater than one second at room temperature independent of power fluctuations.

26. The circuit as recited in claim 25, wherein the circuit forms a portion of a RFID device.

27. A timing circuit in an RFID device, the circuit comprising:

a charge storage portion;

a logic coupled to the charge storage portion, the logic to store a SLEEP state;

an antenna coupled to the logic, the antenna to receive a SLEEP command which places the RFID device in the SLEEP state which is retained by the RFID device even after a loss of power to the RFID device.

28. A circuit as in claim 27 wherein the RFID device is a passive RFID tag.

29. A circuit as in claim 28 wherein the loss of power occurs when a reader is frequency hopping.