Nonplanar device with stress incorporation layer and method of fabrication

• US 20050242406A1
• Filed: 06/30/2005
• Published: 11/03/2005
• Est. Priority Date: 06/27/2003
• Status: Active Grant

• Current Assignee: Been-Yih Jin, Brian S. Doyle, Robert S. Chau, Scott A. Hareland, Suman Datta
• Original Assignee: Been-Yih Jin, Brian S. Doyle, Robert S. Chau, Scott A. Hareland, Suman Datta
• Inventors: Jin, Been-Yih, Chau, Robert S., Doyle, Brian S., Hareland, Scott A., Datta, Suman
• Granted Patent: US 7,241,653 B2
• Time in Patent Office: Days
• US Class Current: 257/401
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7849 the means being provided under the channel
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.

Claims

1-29. -29. (canceled)

30. A method of forming a semiconductor device comprising:

forming a semiconductor body having a top surface and laterally opposite sidewalls on a substrate;

forming a gate dielectric on said top surface of said semiconductor body and on said laterally opposite sidewalls of said semiconductor body;

forming a gate electrode on said gate dielectric and adjacent to said gate dielectric on said laterally opposite sidewalls of said semiconductor body; and

forming a thin film adjacent to said semiconductor body wherein said thin film produces a stress in said semiconductor body.

31. The method of claim 30, further comprising forming said thin film beneath said semiconductor body beneath said gate electrode.

32. The method of claim 30, wherein said substrate is a semiconductor substrate.

33. A method of forming a semiconductor device comprising:

forming a semiconductor body having a top surface and laterally opposite sidewalls on a substrate;

forming a gate dielectric on said laterally opposite sidewalls of said semiconductor body;

forming a gate electrode over said top surface of said semiconductor body and adjacent to said gate dielectric on said laterally opposite sidewalls of said semiconductor body; and

forming a thin film adjacent to said semiconductor body wherein said thin film produces a stress in said semiconductor body.

34. The method of claim 33, wherein the substrate is an insulating substrate.

35. The method of claim 34, wherein the insulating substrate comprises an insulating film formed on a silicon substrate, and the insulating film comprises a material selected from the group consisting of silicon dioxide, silicon nitride, nitride, oxide, and sapphire.

36. The method of claim 33, wherein the substrate is a semiconductor substrate comprising a material selected from the group consisting of silicon and gallium arsenide.

37. The method of claim 33, further comprising forming an insulating layer over said top surface of said semiconductor body and beneath said gate electrode formed over said top surface of said semiconductor body.

38. The method of claim 33, wherein the insulating layer comprises silicon nitride.

39. The method of claim 33, wherein said film is to have stress.

40. A method of forming a semiconductor device comprising:

forming a semiconductor body having a top surface and laterally opposite sidewalls on a substrate;

forming a gate dielectric on said laterally opposite sidewalls of said semiconductor body;

forming a gate electrode over said top surface of said semiconductor body and adjacent to said gate dielectric on said laterally opposite sidewalls of said semiconductor body; and

removing a portion of said substrate underneath said semiconductor body and beneath said gate electrode to expose a portion of said semiconductor body; and

forming an insulating film beneath said exposed portion, said film to produce stress in said semiconductor body beneath said gate electrode.

41. The method of claim 40, wherein forming said film comprises using a vapor deposition technique.

42. The method of claim 40, wherein said film is to produce compressive stress in said semiconductor body beneath said gate electrode.

43. The method of claim 42, wherein said film is to have tensile stress.

44. The method of claim 40, wherein said film is to produce tensile stress in said semiconductor body beneath said gate electrode.

45. The method of claim 44, wherein said film is to have compressive stress.

46. The method of claim 40, wherein said film comprises silicon nitride.

47. The method of claim 40, further comprising oxidizing said exposed portion of said semiconductor body after removing said portion of said substrate and prior to forming said film.

48. A method of forming a semiconductor device comprising:

patterning a monocrystalline silicon film formed on a substrate into a silicon body having a top surface opposite a bottom surface formed on said substrate, and a first and second laterally opposite sidewalls;

forming a gate dielectric layer on said top surface of said silicon body and on said sidewalls of said silicon body;

depositing a gate material over said silicon body and over said substrate;

patterning said gate material to form a gate electrode on said gate dielectric layer on said top surface of said silicon body and adjacent to said gate dielectric on said sidewalls of said silicon body, said gate electrode having laterally opposite sidewalls which run perpendicular to said laterally opposite sidewalls of said silicon body;

forming a pair of source/drains regions in said silicon body on opposite sides of said laterally opposite sidewalls of said gate electrode, wherein the region between said source/drain regions in said silicon body forms a channel region;

removing a portion of said substrate from underneath a portion of said channel region of said silicon body and beneath a portion of said source and drain regions of said silicon body; and

forming an insulating film beneath said exposed portion of said silicon body beneath said gate electrode and beneath said exposed portion of said source and drain regions beneath said gate electrode, said film to produce stress in said silicon body.

49. The method of claim 48, wherein said insulating film is to produce tensile stress in said channel region.

50. The method of claim 48, wherein said insulating film is to produce compressive stress in said channel region.

51. A method of forming a semiconductor device comprising:

patterning a monocrystalline silicon film formed on a substrate into a silicon body having a top surface opposite a bottom surface formed on said substrate, and a first and second laterally opposite sidewalls;

forming a gate dielectric layer on said sidewalls of said silicon body;

depositing a gate material over said silicon body and over said substrate;

patterning said gate material to form a gate electrode adjacent to said gate dielectric on said sidewalls of said silicon body, said gate electrode having laterally opposite sidewalls which run perpendicular to said laterally opposite sidewalls of said silicon body;

forming a pair of source/drains regions in said silicon body on opposite sides of said laterally opposite sidewalls of said gate electrode, wherein the region between said source/drain regions in said silicon body forms a channel region;

removing a portion of said substrate from underneath a portion of said channel region of said silicon body and beneath a portion of said source and drain regions of said silicon body; and

forming an insulating film beneath said exposed portion of said silicon body beneath said gate electrode and beneath said exposed portion of said source and drain regions beneath said gate electrode, said film to produce stress in said silicon body.

52. The method of claim 51, wherein said insulating film is to produce tensile stress in said silicon body.

53. The method of claim 51, wherein said insulating film is to produce compressive stress in said silicon body.

54. The method of claim 51, wherein said insulating film is to have stress.

55. The method of claim 51, further comprising forming said insulating film adjacent to said laterally opposite sidewalls of said silicon body and said laterally opposite sidewalls of said gate electrode.

56. A semiconductor device comprising:

a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate;

a gate dielectric formed on said laterally opposite sidewalls of said semiconductor body;

a gate electrode formed over said top surface of said semiconductor body and adjacent to said gate dielectric on said laterally opposite sidewalls of said semiconductor body; and

a film formed beneath said semiconductor body wherein said film produces a stress in said semiconductor body.

57. The device of claim 56, further comprising an oxide layer disposed between said semiconductor body and said film.

58. The device of claim 56, further comprising an insulating layer formed between said top surface of said semiconductor body and said gate electrode formed over said top surface of said semiconductor body.

59. The device of claim 56, wherein said film is to have stress.