System monitor in a programmable logic device

• US 20050242836A1
• Filed: 04/30/2004
• Published: 11/03/2005
• Est. Priority Date: 04/30/2004
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Goetting, F. Erich, Quinn, Patrick J., Jennings, John K., Collins, Anthony J.
• Granted Patent: US 7,138,820 B2
• Time in Patent Office: Days
• US Class Current: 326/39
• CPC Class Codes: G01R 31/3167 Testing of combined analog and digital circuits testing ADC's H03M1/1071
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]
• CPC Class Codes: H03K 19/17732 Macroblocks

Abstract

Method and apparatus for a system monitor (20) embedded in a programmable logic device (10, 50, 60) are described. The system monitor (20) includes a dynamic reconfiguration port interface (205) for configuring or reconfiguring the system monitor (20) during operation thereof. The system monitor (20) includes an analog-to-digital converter (200) which is reconfigurable responsive to input via a dynamic reconfiguration port (201).

Claims

1. A programmable logic device, comprising:

a system monitor, the system monitor including;

channel inputs including analog inputs;

selection circuitry coupled to the channel inputs, the selection circuitry having a channel output;

an analog-to-digital converter having an analog input and a digital output;

an interface having storage devices, the storage devices for storing control information and data, the interface including a dynamic reconfiguration port and control logic;

the analog-to-digital converter configurable responsive to a first portion of the control information;

the selection circuitry configured to selectively couple a channel input of the channel inputs to the channel output responsive to a second portion of the control information; and

the analog-to-digital converter coupled to the channel output at the analog input and coupled at the digital output to the storage devices.

2. The programmable logic device, according to claim 1, wherein the second portion of the control information comprises channel selection information.

3. The programmable logic device, according to claim 2, wherein the first portion of the control information comprises averaging information.

4. The programmable logic device, according to claim 2, wherein the control logic includes a channel sequencer.

5. The programmable logic device, according to claim 4, wherein the second portion of the control information comprises sequence information.

6. The programmable logic device, according to claim 1, wherein the first portion of the control information comprises calibration information.

7. The programmable logic device, according to claim 1, wherein the storage devices comprise data registers and control registers.

8. The programmable logic device, according to claim 7, wherein the control registers comprise alarm registers for storing threshold values.

9. The programmable logic device, according to claim 8, wherein the control logic is configured to compare the threshold values stored in the alarm registers with data values stored in the data registers.

10. The programmable logic device, according to claim 7, wherein the control registers comprise configuration registers for storing configuration information.

11. The programmable logic device, according to claim 1, further comprising at least one temperature sensor coupled to the selection circuitry via a portion of the channel inputs.

12. The programmable logic device, according to claim 1, further comprising at least one supply monitor coupled to the selection circuitry via a portion of the channel inputs.

13. The programmable logic device, according to claim 1, further comprising at least one self-check calibration sensor coupled to the selection circuitry via a portion of the channel inputs.

14. The programmable logic device, according to claim 1, wherein the dynamic reconfiguration port is configured for dynamic reconfiguration of the system monitor including reading and writing to a portion of the storage devices during operation of the system monitor.

15. The programmable logic device, according to claim 14, wherein the system monitor is embedded in a field programmable gate array.

16. The programmable logic device, according to claim 15, wherein the control logic comprises a test data interface for accessing the data stored in the storage devices.

17. The programmable logic device, according to claim 16, wherein the storage devices are registers.

18. The programmable logic device, according to claim 17, wherein bit positions in the registers are used to select an operational mode of the system monitor input from a unipolar mode and a bipolar mode.

19. The programmable logic device, according to claim 17, wherein bit positions in the registers are used to select a mode of the system monitor input from an event driven sampling mode and a continuous sampling mode.

20. The programmable logic device, according to claim 1, wherein the analog-to-digital converter is configured to receive a start clock signal to define a sampling instant for an event-sampling mode.

21. The programmable logic device, according to claim 1, wherein the channel inputs comprise internal and external channel inputs.

22. The programmable logic device, according to claim 21, wherein the channel inputs comprise differential inputs;

and wherein sources for the channel inputs are selected from differential sources and single-ended sources.

23. The programmable logic device, according to claim 1, wherein the control logic is configured to divide down a first clock signal of the dynamic reconfiguration port to provide a second clock signal at a lower frequency for operation of the analog-to-digital converter.

24. The programmable logic device, according to claim 23, further comprising an oscillator configured to provide an oscillator signal.

25. The programmable logic device, according to claim 24, wherein the control logic is configured to use the oscillator signal to provide the second clock signal responsive to the first clock signal not being present.

26. The programmable logic device, according to claim 1, wherein output from the digital output is responsive to a stepwise transfer function.

27. The programmable logic device, according to claim 1, wherein the control logic is configured to provide at least one over temperature signal.

28. The programmable logic device, according to claim 27, wherein the control logic is configured to receive an initialization complete signal from the field programmable gate array and to initiate monitoring of temperature of the field programmable gate array responsive to the initialization complete signal.

29. A method for configuration of a system monitor, comprising:

resetting a system monitor after powering up a host programmable logic device;

waiting for the programmable logic device to initialize;

activating reference generation circuits and at least one temperature sensor; and

entering a temperature sensing mode of the system monitor, the temperature sensing mode being independent of configuration of configuration memory cells of the programmable logic device.

30. The method, according to claim 29, further comprising:

completing an initial configuration of the programmable logic device, the initial configuration of the programmable logic device including obtaining information, the information including configuration information for the system monitor; and

entering an operational mode of the system monitor responsive to completion of the initial configuration.

31. The method, according to claim 30, further comprising:

suspending operation of the programmable logic device; and

reconfiguring a portion of the system monitor from other configuration information obtained via a dynamic reconfiguration port.

32. The method, according to claim 31, wherein the portion of the system monitor is reconfigured with a configuration write for the temperature sensing mode.

33. The method, according to claim 32, wherein during the temperature sensing mode only temperature is monitored.

34. The method, according to claim 30, further comprising:

maintaining operation of the programmable logic device; and

reconfiguring a portion of the system monitor from other configuration information obtained via a dynamic reconfiguration port.

35. The method, according to claim 30, wherein the operational mode is a continuous sampling mode.

36. The method, according to claim 30, wherein the operational mode is an event driven sampling mode.

37. The method, according to claim 30, wherein the operational mode is a sequence mode.

38. The method, according to claim 37, further comprising obtaining samples on channels.

39. The method, according to claim 38, wherein averaging is active on at least one of the channels.

40. The method, according to claim 39, wherein the at least one of the channels is used to obtain samples for an averager to provide an averaged result.

41. The method, according to claim 40, wherein the averaged result comprises multiple passes through a sequence of the channels.

42. The method, according to claim 41, wherein the at least one of the channels is used to obtain a calibration offset value.

43. The method, according to claim 42, further comprising calibrating the system monitor using the calibration offset value.

44. The method, according to claim 43, wherein the system monitor comprises an analog-to-digital converter which is calibrated using the calibration offset value.

45. The method, according to claim 30, further comprising calibrating the system monitor with a calibration coefficient, the calibration coefficient being stored in a register of the system monitor.

46. The method, according to claim 45, wherein the calibrating of the system monitor is a single point temperature calibration.

47. A programmable logic device, comprising:

a system monitor, the system monitor including;

channel inputs including analog inputs;

selection circuitry coupled to the channel inputs, the selection circuitry having a channel output;

an analog-to-digital converter having an analog input and a digital output;

an interface having storage devices, the storage devices for storing control information and data, the interface including control logic and interface logic;

the analog-to-digital converter configurable responsive to a first portion of the control information;

the selection circuitry configured to selectively couple a channel input of the channel inputs to the channel output responsive to a second portion of the control information; and

the analog-to-digital converter coupled to the channel output at the analog input and coupled at the digital output to the storage devices.

48. The programmable logic device, according to claim 47, wherein the interface logic includes a dynamic reconfiguration port.

49. A system monitor circuit in an integrated circuit comprising:

an analog-to digital converter (ADC) configured to monitor a plurality of sensors;

a calibration circuit for calibrating an output of the ADC using a set value in a first register;

a filter circuit for filtering an output of the calibration circuit or an output of the ADC; and

a alarm circuit configured to determine an alarm condition by comparing the output of the calibration circuit or an output of the ADC or an output of the filter circuit with a set value in a second register.

50. The system monitor circuit of claim 49 further comprising:

a microcontroller coupled to the ADC.

51. The system monitor circuit of claim 50 wherein the microcontroller is coupled to a read-only memory.

52. The system monitor circuit of claim 50 wherein the microcontroller is coupled to a random access memory.

53. The system monitor circuit of claim 49 further comprising:

a hardwired PicoBlaze microcontroller coupled to a memory, the memory including the fist and second registers.

54. The system monitor circuit of claim 49 further comprising:

a memory coupled to a channel sequencer, the channel sequencer selecting a channel of the ADC for automatic monitoring.