Light emitting panel and light emitting display

• US 20050243039A1
• Filed: 04/21/2005
• Published: 11/03/2005
• Est. Priority Date: 04/29/2004
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Mobile Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Kwak, Won-Kyu
• Granted Patent: US 7,592,982 B2
• Time in Patent Office: Days
• US Class Current: 345/76
• CPC Class Codes: G09G 2300/0804 Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
• CPC Class Codes: G09G 2300/0814 used for selection purposes, e.g. logical AND for partial update
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0852 being a dynamic memory with more than one capacitor
• CPC Class Codes: G09G 2300/0861 with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
• CPC Class Codes: G09G 2310/0235 Field-sequential colour display
• CPC Class Codes: G09G 2310/0262 The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: H10K 59/121 characterised by the geometry or disposition of pixel elements
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/1216 the pixel elements being capacitors
• CPC Class Codes: H10K 59/35 comprising red-green-blue [RGB] subpixels

Abstract

A display device having components that are efficiently arranged in a pixel. A pixel circuit includes a capacitor for charging a voltage which corresponds to a data signal transmitted from a data line. A first transistor of the pixel circuit outputs a current corresponding to the voltage charged in the capacitor. A plurality of emit elements emit a light corresponding to the current outputted from the driving transistor. A plurality of emit control transistors are coupled between the first transistor and the plurality of emit elements. The emit control transistors include a plurality of semiconductor layers having inner resistances that are substantially the same as each other.

Claims

1. A display device comprising a plurality of scan lines for transmitting select signals, a plurality of data lines for transmitting data signals, and a plurality of pixel circuits coupled to the scan lines and the data lines, wherein

at least one of the pixel circuits comprises:

a capacitor for charging a voltage which corresponds to one of the data signals transmitted from a corresponding one of the data lines;

a driving transistor for outputting a current corresponding to the voltage charged in the capacitor;

a plurality of emit elements for emitting a light corresponding to the current outputted from the driving transistor; and

a plurality of emit control transistors coupled between the driving transistor and the plurality of emit elements,

wherein the emit control transistors comprise a plurality of semiconductor layers having inner resistances that are substantially the same as each other.

2. The display device of claim 1, wherein a ratio of a length and a width of each of the semiconductor layers is substantially the same as those of other ones of the semiconductor layers.

3. The display device of claim 2, wherein two emit elements among the plurality of emit elements respectively emit one light among a red light, a green light, and a blue light, in response to the current outputted from the driving transistor.

4. The display device of claim 3, wherein the length of each of the semiconductor layers forming a corresponding one of the emit control transistors includes a length of a source area, a length of a channel area, and a length of a drain area of the corresponding one of the emit control transistors.

5. The display device of claim 4, wherein the width of each of the semiconductor layers forming the corresponding one of the emit control transistors is measured in a direction that is substantially perpendicular to a direction in which the length of the semiconductor layer is measured.

6. The display device of claim 2, wherein at least two semiconductor layers among the plurality of semiconductor layers are substantially parallel to each other.

7. A display device comprising a plurality of scan lines for transmitting select signals, a plurality of data lines for transmitting data signals, and a plurality of pixel circuits coupled to the scan lines and the data lines, wherein

at least one of the pixel circuits arranged in a pixel area comprises:

first, second, and third emit elements comprising pixel electrodes to which a current is applied, for emitting light corresponding to the applied current; and

first, second, and third semiconductor layers respectively coupled to pixel electrodes of the first, second, and third emit elements through first, second, and third contact holes; and

first, second, and third control electrode lines being insulated and crossing the first, second, and third semiconductor layers and being substantially parallel to each other,

wherein ratios of a length and a width of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are substantially the same as each other.

8. The display device of claim 7, wherein the first semiconductor layer forms a first emit control transistor having an insulated channel area which crosses the first control electrode line;

the second semiconductor layer forms a second emit control transistor having an insulated channel area which crosses the second control electrode line; and

the third semiconductor layer forms a third emit control transistor having an insulated channel area which crosses the third control electrode line.

9. The display device of claim 8, wherein the length of each of the first, second, and third semiconductor layers includes a length of a source area, a length of the channel area, and a length of a drain area of a corresponding one of the first, second, and third emit control transistors.

10. The display device of claim 9, wherein the width of each of the first, second, and third semiconductor layers is measured in a direction substantially perpendicular to a direction in which the length of the corresponding one of the first, second, and third semiconductor layers is measured.

11. A display device comprising a plurality of scan lines for transmitting select signals, a plurality of data lines for transmitting data signals, and a plurality of pixel circuits coupled to the scan lines and the data lines, wherein

at least one of the pixel circuits comprises:

a first capacitor for charging a voltage which corresponds to one of the data signals transmitted from a corresponding one of the data lines;

a first transistor for outputting a current which corresponds to the voltage charged in the first capacitor;

first, second, and third emit elements for emitting a light corresponding to the current outputted from the first transistor; and

first, second, and third emit control transistors respectively coupled between the first transistor and the first, second, and third emit elements,

wherein the first semiconductor layer forming the first emit control transistor is arranged generally symmetrically with the second semiconductor layer forming the second emit control transistor with respect to the third semiconductor layer forming the third emit control transistor.

12. The display device of claim 11, wherein at least two semiconductor layers among the first, second, and third semiconductor layers are substantially parallel to each other.

13. The display device of claim 12, wherein the first, second, and third semiconductor layers forming the first, second, and third emit elements are doped with the same type of impurities.

14. The display device of claim 11, wherein the at least one of the pixel circuits further comprises:

a second transistor coupled between a control electrode of the first transistor and a node between the first transistor and the first, second and third emit control transistors;

a third transistor having a first electrode coupled to a first electrode of the first capacitor and a second electrode coupled to a second electrode of the first capacitor; and

a second capacitor having a first electrode coupled to the second electrode of the third transistor and a second electrode coupled to the control electrode of the first transistor.

15. A display device comprising a plurality of scan lines for transmitting select signals, a plurality of data lines for transmitting data signals, and a plurality of pixel circuits coupled to the scan lines and the data lines and arranged in an array format, wherein

at least one of the pixel circuits arranged in a pixel area comprises:

first, second, and third emit elements comprising pixel electrodes to which a current is applied, for emitting light corresponding to the applied current;

semiconductor layers comprising a first semiconductor layer area coupled to a pixel electrode of the first emit element through a first contact hole, a second semiconductor layer area coupled to a pixel electrode of the second emit element through a second contact hole, and a third semiconductor layer area coupled to a pixel electrode of the third emit element through a third contact hole; and

first, second, and third control electrode lines which are insulated and cross the semiconductor layers and are substantially parallel to each other,

wherein the first semiconductor layer area is arranged generally symmetrically with the third semiconductor layer area with respect to the second semiconductor layer area.

16. The display device of claim 15, wherein at least one semiconductor layer area among the first, second, and third semiconductor layer areas is substantially parallel to at least one of the data lines.

17. The display device of claim 16, wherein at least one semiconductor layer area among the first, second and third semiconductor layer areas is substantially parallel to at least one of the scan lines.