Asynchronous request/synchronous data dynamic random access memory
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Abstract
At page 54, please delete the current abstract and replace it with the following: An integrated circuit memory device comprises a latch circuit to load an address using a first control signal. A first signal level transition of the first control signal is used to load the address. A memory array stores data at a memory location that is based on the address. An output buffer outputs the data after a period of time from the first signal level transition. A register stores a value that specifies between at least a first mode and a second mode. When the value specifies the first mode, the output buffer outputs the data in response to address transitions that occur after the first signal level transition. When the value specifies the second mode, the output buffer outputs data synchronously with respect to an external clock signal.
13 Citations
68 Claims
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1-41. -41. (canceled)
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42. An integrated circuit memory device comprising:
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a latch circuit to load an address using a first control signal, wherein a first signal level transition of the first control signal is used to load the address;
a memory array to store data at a memory location that is based on the address;
an output buffer to output the data after a period of time from the first signal level transition; and
a register to store a value that specifies between at least a first mode and a second mode, wherein;
when the value specifies the first mode, the output buffer outputs the data in response to address transitions that occur after the first signal level transition; and
when the value specifies the second mode, the output buffer outputs data synchronously with respect to an external clock signal. - View Dependent Claims (43, 44, 45, 46, 47, 48, 49, 50)
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51. An integrated circuit memory device comprising:
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a memory array;
a clock buffer to receive an external clock signal;
an input buffer to receive a control signal;
an output buffer to output data in response to the control signal, wherein the data is output after a number of clock cycles from when the control signal is received; and
a register to store a value to indicate a mode of operation of the integrated circuit memory device, the value to indicate whether the integrated circuit memory device operates in at least one of a first mode and a second mode, wherein;
when the value indicates the first mode of operation, the output buffer outputs the data using the external clock signal; and
when the value indicates the second mode of operation, the output buffer outputs the data in response to address transitions. - View Dependent Claims (52, 53, 54, 55, 56)
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57. An integrated circuit memory device comprising:
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a memory array having a plurality of banks to store data;
a clock buffer to receive an external clock signal;
an output buffer to output the data after a period of time from receipt of a transition in a control signal; and
a register to store a value that indicates a mode of operation of the integrated circuit memory device, the mode of operation selected from between at least a synchronous mode of operation and an asynchronous mode of operation, wherein;
when the value indicates the synchronous mode of operation, the output buffer to output the data in response to a transition of the external clock signal; and
when the value indicates the asynchronous mode of operation, the output buffer to output the data in response to the control signal. - View Dependent Claims (58, 59, 60, 61, 62)
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63. A method of operating a memory device having a memory array, the method comprising:
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specifying at least one of a first mode of operation and a second mode of operation;
receiving an address using a first control signal;
accessing data in a location of the memory array specified at least in part by the address;
outputting the data in response to a second control signal that specifies a read transaction;
wherein;
during the first mode of operation, the output buffer is to output the data after a period of time from a transition of the first control signal; and
during the second mode of operation, the output buffer is to output the data after a predetermined number of clock cycles of an external clock signal have transpired from receiving the address, wherein the data is output with reference to transitions of the external clock signal. - View Dependent Claims (64, 65, 66, 67, 68)
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Specification