Network switch and components and method of operation

• US 20050243850A1
• Filed: 06/14/2005
• Published: 11/03/2005
• Est. Priority Date: 08/27/1999
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Calvignac, Jean Louis, Siegel, Michael Steven, Verplanken, Fabrice Jean, Heddes, Marco C., Rao, Sridhar, Gallo, Anthony Matteo, Bass, Brian Mitchell, Youngman, Brian Alan
• Granted Patent: US 7,590,057 B2
• Time in Patent Office: Days
• US Class Current: 370/412
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: H04L 49/15 Interconnection of switching modules
• CPC Class Codes: H04L 49/205 Quality of Service based
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/3036 Shared queuing
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches

Abstract

A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a control point and a plurality of interface processors formed on a semiconductor substrate. The control point and interface processors together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.

Claims

1. A communications device comprising:

a control point processor subsystem; and

a network processor, operatively coupled to said control point processor, including;

N interface processors, N>

1;

a plurality of media interfaces;

a plurality of queues coupling the interfaces to the processors wherein the queues provide channels through which data enters and leaves the processors;

memory that stores data passing through said control processor; and

euqueue/dequeue scheduler responsive to control signal to move data from the memory to a selected queue; and

said control point process or subsystem including;

control point function generator that generates and forwards to one of said plurality of media interfaces a guided frame with information that allows said control point processor subsystem access to registers and memories under control of said network processor.

2. The communications device of claim 1 wherein the information including at least one word of frame control information, one word of software correlation, one or a sequence of guided commands and an end delimeter guided command.

3. The communications device of claim 1 further including a frame control block register operatively coupled to the N interface processors, said frame control block register storing information used to route processed guided frame back tot he control point function generator.

4. The communications device of claim 1 further including a Target Blade Start Of Frame (TB_SOF) queue operatively coupled to the N interface processor and storing Guided Frame to be broadcast.

5. The communications device of claim 1 wherein the control point processor subsystem includes a bus;

an arbiter coupled to said bus;

a CPU coupled to said bus;

a DMA controller coupled to the bus;

a Mailbox and DRAM Interface coupled to the bus;

an interrupt controller interconnecting the CPU and the Mailbox and DRAM interface;

a DRAM arbiter coupled to the N-interface processor and the Mailbox and DRAM Interface; and

a DRAM controller coupled to the DRAM arbiter.

6. The communications device of claim 5 further including at least an interrupt line coupling the N-processor to the Mailbox and DRAM Interface and a communication line interconnecting one of the N-interface processors to the Mailbox and DRAM Interface.

7. The communications device of claim 1 wherein components of the network processor are fabricated on a common substrate.

8. The communications device of claim 7 wherein the control point processor subsystem is fabricated on the common substrate.

9. The communications device of claim 1 wherein the control point processor subsystem is external to a common substrate on which said network processor is fabricated;

and

a communications module interconnects the control point processor subsystem to at least one of the plurality of media interfaces.

10. The communications device of claim 9 wherein the at least one of the plurality of media interfaces includes a first ethernet Medium Access Control, MAC;

and the communications module including;

a second ethernet MAC/PHY coupled to the processor sub-system;

an ethernet PHY coupled to the ethernet MAC/PHY; and

a transmission media coupling the ethernet PHY to the first ethernet MAC.

11. The communications device of claim 10 further including an interconnecting device interconnecting the second ethernet MAC/PHY tot he processor sub-system;

and

a storage operatively connected to said interconnecting device.

12. The communications device of claim 11 wherein the interconnecting device includes a PCI bridge.