Offset spacer formation for strained channel CMOS transistor

• US 20050247986A1
• Filed: 05/06/2004
• Published: 11/10/2005
• Est. Priority Date: 05/06/2004
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Wen-Chin, Ko, Chih-Hsin, Ge, Chung-Hu
• Granted Patent: US 7,321,155 B2
• Time in Patent Office: Days
• US Class Current: 257/411
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

A strained channel transistor and method for forming the the strained channel transistor including a semiconductor rate; a gate dielectric overlying a channel region; a gate rode overlying the gate dielectric; source drain extension regions and source and drain (S/D) regions; wherein a sed dielectric portion selected from the group consisting of r of stressed offset spacers disposed adjacent the gate rode and a stressed dielectric layer disposed over the gate rode including the S/D regions is disposed to exert a strain channel region.

Claims

1. A method of forming a strained channel transistor comprising the steps of:

providing a semiconductor substrate;

forming a gate dielectric over the substrate;

forming a gate electrode on the gate dielectric;

forming doped source/drain extension (SDE) regions adjacent the gate electrode;

forming a first pair of offset liners adjacent the sides of the gate electrode and a pair of offset spacers adjacent the first pair of offset liners;

forming source and drain (S/D) regions according to an ion implantation process;

removing the first pair of offset spacers; and

,

forming one of a pair of stressed offset spacers adjacent the first pair of offset liners and a stressed dielectric layer over the first pair of offset liners including the S/D regions.

2. The method of claim 1, wherein a second pair of offset liners are formed over the first pair of liners prior to the step of forming a pair of stressed offset spacers.

3. The method of claim 1, wherein a portion of the first pair of offset liners are removed to expose a portion of the SDE regions prior to the step of forming a pair of stressed offset spacers.

4. The method of claim 1, wherein the step of forming S/D regions comprises a step of rapid thermal annealing (RTA) following the ion implantation process.

5. The method of claim 1, further comprising the step of forming conductive regions over the S/D regions following forming the pair of stressed offset spacers.

6. The method of claim 1, further comprising step of forming recessed areas over the respective S/D regions prior to the step of forming conductive regions.

7. The method of claim 1, further comprising the step of forming conductive regions over the S/D regions prior to forming the stressed dielectric layer.

8. The method of claim 7, further comprising the step of forming recessed areas over the respective S/D regions prior to the step of forming conductive regions.

9. The method of claim 1, further comprising the step of forming a stressed contact etching stop layer over the gate structure including the pair of stressed offset spacers and the S/D regions following forming the pair of stressed offset spacers.

10. The method of claim 9, wherein the pair of stressed offset spacers, the first pair of offset liners, and the stressed contact etching stop layer are formed of a material selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxide, and combinations thereof.

11. The method of claim 10, wherein the pair of stressed offset spacers and the stressed contact etching stop layer have a stress level up to about 2 GPa.

12. The method of claim 1, wherein the pair of stressed offset spacers and the stressed dielectric layer are formed of a material selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxide, and combinations thereof.

13. The method of claim 12, wherein the pair of stressed offset spacers and the stressed dielectric layer have a stress level up to about 2 GPa.

14. The semiconductor device of claim 1, wherein the gate dielectric is selected from the group consisting of silicon oxide, silicon oxynitride, silicon nitride, a high permittivity dielectric, and combinations thereof.

15. The method of claim 14, wherein the high permittivity dielectric is selected from the group consisting of transition metal oxides, rare earth metal oxides, and combinations thereof.

16. The method of claim 1, wherein the gate electrode comprises a material selected from the group consisting of metals, metal silicides, metal nitrides, doped polysilicon, and combinations thereof.

17. The method of claim 1, wherein the semiconductor substrate is selected from the group consisting of silicon, silicon on insulator (SOI), strained silicon, and silicon-germanium.

30. The strained channel transistor of claim 16, wherein the gate electrode comprises a material selected from the group consisting of metals, metal silicides, metal nitrides, doped-polysilicon, and combinations thereof.

18. A strained channel transistor comprising:

a semiconductor substrate;

a gate dielectric overlying a channel region;

a gate electrode overlying the gate dielectric;

source/drain extension (SDE) regions and source and drain (S/D) regions;

wherein a stressed dielectric portion selected from the group consisting of a pair of stressed offset spacers disposed adjacent the gate electrode and a stressed dielectric layer disposed over the gate electrode including the S/D regions is disposed to exert a strain on the channel region.

19. The strained channel transistor of claim 18, further comprising a pair of offset liners disposed along the sides of the gate electrode.

20. The strained channel transistor of claim 18, wherein a portion of the pair of stressed offset spacers contacts the semiconductor substrate.

21. The strained channel transistor of claim 18, further comprising recessed areas over disposed the respective S/D regions.

22. The strained channel transistor of claim 18, further comprising conductive regions disposed over the S/D regions.

23. The strained channel transistor of claim 18, further comprising a stressed contact etching stop layer disposed over the gate electrode including the pair of stressed offset spacers and the S/D regions.

24. The strained channel transistor of claim 23, wherein the pair of stressed offset spacers and the stressed contact etching stop layer are formed of a material selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxide, and combinations thereof.

25. The strained channel transistor of claim 24, wherein the pair of stressed offset spacers and the stressed contact etching stop layer have a stress level up to about 2 GPa.

26. The strained channel transistor of claim 18, wherein the stressed dielectric portion is formed of a material selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxide, and combinations thereof.

27. The strained channel transistor of claim 26, wherein the stressed dielectric portion has a stress level up to about 2 GPa.

28. The strained channel transistor of claim 18, wherein the gate dielectric is selected from the group consisting of silicon oxide, silicon oxynitride, silicon nitride, a high permittivity dielectric, and combinations thereof.

29. The strained channel transistor of claim 28, wherein the high permittivity dielectric is selected from the group consisting of transition metal oxides, rare earth metal oxides, and combinations thereof.

31. The strained channel transistor of claim 18, wherein the semiconductor substrate is selected from the group consisting of silicon, silicon on insulator (SOI), strained silicon, and silicon-germanium.

32. A strained channel transistor comprising:

a semiconductor substrate;

a gate dielectric overlying a channel region;

a gate electrode overlying the gate dielectric;

recessed source and drain (S/D) regions disposed adjacent opposing sides of the channel region;

wherein a pair of stressed offset spacers are disposed adjacent the sides of the gate electrode to exert a strain on the channel region.

33. The strained channel transistor of claim 32, further comprising a stressed dielectric layer disposed over the gate structure including the pair of stressed offset spacers and the S/D regions.

34. The strained channel transistor of claim 32, further comprising conductive regions disposed over the S/D regions.

36. The strained channel transistor of claim 34, further comprising a stressed dielectric layer disposed over the gate electrode including the pair of stressed offset spacers and the S/D regions.

37. The strained channel transistor of claim 34, further comprising conductive regions disposed over the S/D regions.

39. The strained channel transistor of claim 37, wherein the S/D regions comprise respective recessed regions formed on opposing sides of a channel region.

40. The strained channel transistor of claim 37, further comprising conductive regions disposed over the S/D regions.

41. The strained channel transistor of claim 37, further comprising an offset liner disposed on the sides of the gate electrode.

35. A strained channel transistor comprising:

a semiconductor substrate;

a gate dielectric overlying a channel region;

a gate electrode overlying the gate dielectric;

source and drain (S/D) regions disposed on opposing sides of the channel region;

wherein a pair of stressed offset spacers are disposed adjacent the sides of the gate electrode such that a portion contacts the semiconductor substrate to exert a strain on the channel region.

38. A strained channel transistor comprising:

a semiconductor substrate;

a gate dielectric overlying a channel region;

a gate electrode overlying the gate dielectric;

source and drain (S/D) regions disposed on opposing sides of the channel region;

wherein a stressed dielectric layer is formed over the gate electrode including the S/D regions to exert a strain on the channel region.