DATA TRANSFERRING METHOD

• US 20050248370A1
• Filed: 04/21/2005
• Published: 11/10/2005
• Est. Priority Date: 04/22/2004
• Status: Abandoned Application

• Current Assignee: Novatek Microelectronics Corporation (Novatek Microelectronics Corp Limited)
• Original Assignee: Novatek Microelectronics Corporation (Novatek Microelectronics Corp Limited)
• Inventors: Tang, Alex, Li, Yu-Hsuan, Liu, Yueh-Hsiu
• Application Number:
  US10/907,921
• Publication Number:
  US 20050248370A1
• Time in Patent Office: Days
• US Class Current: 327/58
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: H04L 25/4906 using binary codes
• CPC Class Codes: H04L 25/4917 using multilevel codes

Abstract

A data transferring method for the input interface of a liquid crystal display. In the conventional reduced swing differential signal (RSDS) data transferring method, a pair of data lines can transmit a single bit of data. Thus, more data line pairs are required to transmit more data bits leading to a rapid increase in spatial occupancy and production cost. The present invention permits more data bits to be transmitted for the same number of data lines by converting DC levels into AC levels. With two DC levels provided by two pairs of data lines, a third bit of data can be transmitted. Similarly, with four DC levels provided by four pairs of data lines, seven bit data can be transmitted. Since more data can be transmitted with a given set of data lines, space and production cost is saved.

Claims

1. A method of transferring data through a differential signal data transmission system, comprising the steps of:

selecting a first DC voltage level of a first pair of differential signal sources to serve as a first differential signal, wherein the first pair of differential signal sources generates a first data bit;

selecting a second DC voltage level of a second pair of differential signal sources to serve as a second differential signal, wherein the second pair of differential signal sources generate a second data bit; and

generating a third data bit according to the first differential signal and the second differential signal.

2. The method of claim 1, wherein the third data bit is set to a logic level ‘

0’

when the first DC voltage level is higher than the second DC voltage level and the third data bit is set to a logic level ‘

1’

when the first DC voltage level is lower than the second DC voltage level.

3. A method of transferring data through a differential signal transmission system, wherein the differential signal transmission structure comprises a plurality of pairs of differential signal sources, comprising the steps of:

generating a plurality of additional pairs of differential signal sources according to the two DC voltage levels of every pair of differential signal sources and transmitting a plurality of corresponding pairs of data bits according to the additional pairs of differential signal sources.

4. The method of claim 3, wherein the method further comprises selecting the DC voltage levels of every two pairs of differential signal sources from the additional pairs of differential signal sources to generate extra data bits.

5. A method of transferring data through a differential signal transmission system, wherein the differential signal transmission structure comprises a plurality of pairs of differential signal sources, comprising the steps of:

selecting a first DC voltage level of a first pair of differential signal sources to serve as a first differential signal, wherein the first pair of differential signal sources generates a first data bit;

selecting a second DC voltage level of a second pair of differential signal sources to serve as a second differential signal, wherein the second pair of differential signal sources generates a second data bit;

selecting a third DC voltage level of a third pair of differential signal sources to serve as a third differential signal, wherein the third pair of differential signal sources generate a third data bit;

selecting a fourth DC voltage level of a fourth pair of differential signal sources to serve as a fourth differential signal, wherein the fourth pair of differential signal sources generate a fourth data bit;

generating a fifth data bit according to the first differential signal and the second differential signal;

generating a sixth data bit according to the third differential signal and the fourth differential signal;

generating a seventh data bit according to a fifth DC voltage level of the first differential signal and the second differential signal and a sixth DC voltage level of the third differential signal and the fourth differential signal.

6. The method of claim 5, wherein the fifth data bit is set to a logic level ‘

0’

when the first DC voltage level is higher than the second DC voltage level and the fifth data bit is set to a logic level ‘

1’

when the first DC voltage level is lower than the second DC voltage level.

7. The method of claim 5, wherein the sixth data bit is set to a logic level ‘

0’

when the third DC voltage level is higher than the fourth DC voltage level and the sixth data bit is set to a logic level ‘

1’

when the third DC voltage level is lower than the fourth DC voltage level.

8. The method of claim 5, wherein the seventh data bit is set to a logic level ‘

0’

when the fifth DC voltage level is higher than the sixth DC voltage level and the seventh data bit is set to a logic level ‘

1’

when the fifth DC voltage level is lower than the sixth DC voltage level.